CYRF6936
Document #: 38-16015 Rev. *G
Page 13 of 40
Mnemonic
CHANNEL_ADR
Address
0x00
Bit
7
6
5
4
3
2
1
0
Default
-
1
0
0
1
0
0
0
Read/Write
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
Not Used
Channel
Bit 7
Not Used.
Bits 6:0
This field selects the channel. 0x00 sets 2400 MHz; 0x62 sets 2498 MHz. Values above 0x62 are not valid. The default channel
is a fast channel above the frequency typically used in non-overlapping WiFi systems. Any write to this register impacts the time
it takes the synthesizer to settle.
fast (100
μs) - 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 96
medium (180
μs) - 2 4 8 10 14 16 20 22 26 28 32 34 38 40 44 46 50 52 56 58 62 64 68 70 74 76 78 80 82 84 86 88 90 92 94
slow (270
μs) - 1 5 7 11 13 17 19 23 25 29 31 35 35 37 41 43 47 49 53 55 59 61 65 67 71 73 75 77 79 81 83 85 87 89 91 93 95 97
Usable channels subject to regulation.
Do not access or modify this register during Transmit or Receive.
Mnemonic
TX_LENGTH_ADR
Address
0x01
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
TX Length
Bits 7:0
This register sets the length of the packet to be transmitted. A length of zero is valid, and transmits a packet with SOP, length
and CRC16 fields (if enabled), but no data field. Packet lengths of more than 16 bytes require that some data bytes be written
after transmission of the packet has begun. Typically, length is updated prior to setting TX GO. The maximum packet length for
all packets is 40 bytes except for framed 64 chip DDR where the maximum packet length is 16 bytes.
Maximum packet length is limited by the delta between the transmitter and receiver crystals of 60 ppm or better.
Mnemonic
TX_CTRL_ADR
Address
0x02
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
TX GO
TX CLR
TXB15
IRQEN
TXB8
IRQEN
TXB0
IRQEN
TXBERR
IRQEN
TXC
IRQEN
TXE
IRQEN
Bit 7
Start Transmission. Setting this bit triggers the transmission of a packet. Writing ‘0’ to this flag has no effect. This bit is cleared
automatically at the end of packet transmission. The transmit buffer may be loaded either before or after setting this bit. If data
is loaded after setting this bit, the length of time available to load the buffer depends on the starting state (sleep, idle or synth),
the length of the SOP code, the length of preamble, and the packet data rate. For example, if starting from idle mode on a fast
channel in 8DR mode with 32 chip SOP codes the time available is 100
μs (synth start) + 32 μs (preamble) + 64 μs (SOP
length) + 32
μs (length byte) = 228 μs. If there are no bytes in the TX buffer at the end of transmission of the length field, a
TXBERR IRQ occurs.
Bit 6
Clear TX Buffer. Writing ‘1’ to this register clears the transmit buffer. Writing ‘0’ to this bit has no effect. The previous packet (16
or fewer bytes) may be retransmitted by setting TX GO and not setting this bit.
Bit 5
Buffer Not Full Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Bit 4
Buffer Half Empty Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Bit 3
Buffer Empty Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Bit 2
Buffer Error Interrupt Enable. See TX_IRQ_STATUS_ADR for description.
Bit 1
Transmission Complete Interrupt Enable. TXC IRQEN and TXE IRQEN must be set together. See TX_IRQ_STATUS_ADR for
description.
Bit 0
Transmit Error Interrupt Enable. TXC IRQEN and TXE IRQEN must be set together. See TX_IRQ_STATUS_ADR for
description.
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