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PCA9673D Datasheet(PDF) 17 Page - NXP Semiconductors

Part # PCA9673D
Description  Remote 16-bit I/O expander for Fm I2C-bus with interrupt and reset
PDF  33 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PCA9673D Datasheet(HTML) 17 Page - NXP Semiconductors

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PCA9673_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 1 February 2007
17 of 33
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt and reset
10. Application design-in information
10.1 Bidirectional I/O expander applications
In the 8-bit I/O expander application shown in Figure 24, P00 and P01 are inputs, and P02
to P07 are outputs. When used in this configuration, during a write, the input (P00 and
P01) must be written as HIGH so the external devices fully control the input ports. The
desired HIGH or LOW logic levels may be written to the I/Os used as outputs (P02 to
P07). During a read, the logic levels of the external devices driving the input ports (P00
and P01) and the previous written logic level to the output ports (P02 to P07) will be read.
The GPIO also has an interrupt line (INT) that can be connected to the interrupt logic of
the microprocessor. By sending an interrupt signal on this line, the remote I/O informs the
microprocessor that there is incoming data or a change of data on its ports without having
to communicate via the I2C-bus.
10.2 High current-drive load applications
The GPIO has a maximum sinking current of 25 mA per bit. In applications requiring
additional drive, two port pins in the same octal may be connected together to sink up to
50 mA current. Both bits must then always be turned on or off together. Up to 8 pins (one
octal) can be connected together to drive 200 mA.
Fig 24. Bidirectional I/O expander application
002aac310
VDD
temperature sensor
battery status
control for latch
control for switch
control for audio
control for camera
control for MP3
P00
P01
P02
P03
P04
P05
P06
P07
VDD
SDA
SCL
INT
AD0
AD1
CORE
PROCESSOR
VDD
RESET
Fig 25. High current-drive load application
002aac311
VDD
P00
P01
P02
P03
P04
P05
P06
P07
VDD
SDA
SCL
INT
CORE
PROCESSOR
VDD
LOAD
AD0
AD1
RESET



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