PIC16F87 datasheet(18/24 Pages) MICROCHIP

18 / 24 page

PIC16F87/88

DS39607B-page 18

 2002 Microchip Technology Inc.

7.0

PROGRAM MODE ELECTRICAL CHARACTERISTICS

TABLE 7-1:

TIMING REQUIREMENTS FOR PROGRAM MODE

AC/DC CHARACTERISTICS

POWER SUPPLY PINS

Standard Operating Procedure (unless otherwise stated)

Operating Temperature

≤ TA ≤ +70°C

Operating Voltage

2.0V

≤ VDD ≤ 5.5V

Characteristics

Sym

Min

Typ

Max

Units

Conditions/Comments

General

VDD level for Begin Erase, Begin

Program operations and EECON1

writes of program memory

VDD

2.0

—

5.5

VDD level for Begin Erase, Begin

Program operations and EECON1

writes of data memory

VDD

2.0

—

5.5

VDD level for Bulk Erase, Chip Erase,

and Begin Program operations of

program and data memory

VDD

4.5

—

5.5

Begin Programming Only cycle time

tprog1

—

Externally Timed, > 4.5V

—

Externally Timed, < 4.5V

Begin Erase

tprog2

—

Externally Timed, > 4.5V

—

Externally Timed, < 4.5V

Bulk Erase cycle time

tprog3

—

Externally Timed

Chip Erase cycle time

tprog4

—

Internally Timed

High voltage on MCLR and

RA4/T0CKI for Program mode entry

VIHH

VDD + 3.5

—

13.5

MCLR rise time (VSS to VHH) for

Program mode entry

tVHHR

—

1.0

µs

(RB6, RB7) input high level

VIH10.8 VDD

—

Schmitt Trigger input

(RB6, RB7) input low level

VIL10.2 VDD

—

Schmitt Trigger input

RB<7:4> setup time before MCLR

↑

(Program mode selection pattern

setup time)

tset0

100

—

RB<7:4> hold time after MCLR

↑

(Program mode selection pattern

setup time)

thld0

—

µs

Serial Program

Data in setup time before clock

↓

tset1

100

—

Data in hold time after clock

↓

thld1

100

—

Data input not driven to next clock

input (delay required between

command/data or command/

command)

tdly1

1.0

—

µs2.0V ≤ VDD < 4.5V

100

—

4.5V

≤ VDD ≤ 5.5V

Delay between clock

↓ to clock↑

of next command or data

tdly2

1.0

—

µs2.0V ≤ VDD < 4.5V

100

—

4.5V

≤ VDD ≤ 5.5V

Clock

↑ to data out valid

(during read data)

tdly3

—

Setup time between VDD rise and

MCLR rise

tpu

tset0

—

250

µs

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