CS42L51 datasheet(21/88 Pages) CIRRUS

21 / 88 page

DS679F1

CS42L51

14. After powering up the CS42L51, RESET should be held low after the power supplies and clocks are

settled.

15. See “Example System Clock Frequencies” on page 79 for typical MCLK frequencies.

16. See

17. “Master” on page 39

18. “MCLK” refers to the external master clock applied.

Master Mode (Note 17)

Output Sample Rate (LRCK)

All Speed Modes

(Note 17)

-Hz

LRCK Duty Cycle

SCLK Frequency

1/tP

64•Fs

SCLK Duty Cycle

LRCK Edge to SDOUT MSB Output Delay

td(MSB)

-52

SDOUT Setup Time Before SCLK Rising Edge

ts(SDO-SK)

SDOUT Hold Time After SCLK Rising Edge

th(SK-SDO)

SDIN Setup Time Before SCLK Rising Edge

ts(SD-SK)

SDIN Hold Time After SCLK Rising Edge

Parameters

Symbol

Min

Max

Units

MCLK

128

-----------------

th(SK-SDO)

ts(SD-SK)

MSB

MSB-1

LRCK

SCLK

SDOUT

SDIN

td(MSB)

ts(LK-SK)

ts(SDO-SK)

Figure 4. Serial Audio Interface Slave Mode Timing

th(SK-SDO)

ts(SD-SK)

MSB

MSB-1

LRCK

SCLK

SDOUT

SDIN

td(MSB)

ts(SDO-SK)

Figure 5. Serial Audio Interface Master Mode Timing

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