©2003 -Copyright by AverLogic Technologies, Corp.

1-F-PMK008-0001

Function Description

The asynchronous dual-port SRAMs allow fully independent access to any memory location from

both ports without the need of an additional discrete logic. There are separate address, data and control

signals for each port. They can be utilized as either a standalone 8/9/16/18-bit dual-port static RAM or

as a MASTER/SLAVE cascade form in systems requiring 32/36-bit or greater word widths through pin

S

M/

. Master and slave devices provide two independent ports with separate control, address and I/O

pins that permit independent, error-free and asynchronous access for reads and writes to any location in

the memory. It is the solution for applications requiring shared or buffered data such as cache memory

write enable (

W

R/

provided to block the port trying to access the same cell location currently being accessed by the other

port. The AL5DAxxxx series are high speed asynchronous CMOS dual-port SRAMs configured as

For more information regarding AL5DAxxxx asynchronous Dual-Port SRAM or other AverLogic

products, please contact us, your local authorized representatives or visit our web site.

Applications

! Cellular Base Stations

! Multi-protocol Routers

! Internet Appliance

! ATM

! Ethernet

! LAN/WAN Switches

! Hubs

! PBXs

! RAIDs (Storage Networks)

! Set-top Boxes

! Video Conferencing

! Graphics Accelerators

! Audio/Video Editing

! Ultrasound Imaging

! Satellite Encoders

! Cable Modems

! Flight Simulators

! High-end Printing Servers

! Call Distribution Systems

! Fiber Channel Line Boards

! Aerospace Instrumentation

! Industrial Controls

! Any circuit where data must be passed

between different processors

AverLogic Technologies Corp.

AverLogic Technologies, Inc.