© 1996 Microchip Technology Inc.

DS20040J-page 5

59C11

2.8

WRITE All (WRAL)

The entire chip will be written with the data specified in

that command. The WRAL cycle is completely self-

timed and commences after the last data bit (D0) has

been clocked in. WRAL takes 15 ms maximum.

Note:

The WRAL does not include an automatic

ERASE cycle for the chip. Therefore, the

WRAL instruction must be preceded by an

ERAL instruction and the chip must be in

the EWEN status in both cases.

The

WRAL instruction is used for testing and/or

device initialization.

FIGURE 2-1:

READ MODE

FIGURE 2-2:

WRITE MODE

CLK

CS

DI

DO

OPCODE

SB

AN

A0

X

HIGH - Z

NEW INSTRUCTION

OR STANDBY (CS = 0)

NOTE:

ORGANIZATION

AN

DN

128 x 8

A6

64 x 16

A5

1

0X

1

X

X

D0

DN

D7

D15

0

CLK

CS

DI

DO

RDY/BSY

OPCODE

SB

X

AN

A0

XX

X

DN

D0

HIGH - Z

NEW INSTRUCTION

OR STANDBY (CS = 0)

NOTE:

ORGANIZATION

AN

DN

128 x 8

A6

D7

64 x 16

A5

D15

1

X1

X

X