MC13783 datasheet(21/50 Pages) FREESCALE

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Functional Description

MC13783 Technical Data, Rev. 3.4

Freescale Semiconductor

Figure 4. SPI Interface Timing Diagram

Table 6. SPI Interface Timing Specifications

Parameter

Description

T min (ns)

Tselsu

Time CS has to be high before the first rising edge of CLK

Tselhld

Time CS has to remain high after the last falling edge of CLK

Tsellow

Time CS has to remain low between two transfers

Tclkper

Clock period of CLK1

1 Equivalent to a maximum clock frequency of 20 MHz.

Tclkhigh

Part of the clock period where CLK has to remain high

Tclklow

Part of the clock period where CLK has to remain low

Twrtsu

Time MOSI has to be stable before the next rising edge of CLK

Twrthld

Time MOSI has to remain stable after the rising edge of CLK

Trdsu

Time MISO will be stable before the next rising edge of CLK

Trdhld

Time MISO will remain stable after the falling edge of CLK

Trden

Time MISO needs to become active after the rising edge of CS

Trddis

Time MISO needs to become inactive after the falling edge of CS

Table 7. SPI Interface Logic IO Specifications

Parameter

Condition

Min

Max

Units

Input High CS, MOSI, CLK

0.7*VCC

VCC+0.5

Input Low CS, MOSI, CLK

0.3*VCC

Output Low MISO, INT

Output sink 100

μA0

0.2

Output High MISO, INT

Output source 100

μA

VCC-0.2

VCC

Note:

VCC refers to PRIVCC and SECVCC respectively.

CLK

selsu

selhld

clkper

clkhigh

clklow

MOSI

MISO

wrtsu

wrthld

rdsu

rddis

rden

rdhld

sellow

MC13783 Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc

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