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PPC405GPR-3JB333 Datasheet(PDF) 47 Page - Applied Micro Circuits Corporation |
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PPC405GPR-3JB333 Datasheet(HTML) 47 Page - Applied Micro Circuits Corporation |
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47 / 57 page ![]() 405GPr – Power PC 405GPr Embedded Processor AMCC 47 Revision 2.04 – September 7, 2007 Data Sheet Notes: 1. In all of the following I/O Specifications tables a timing values of “na” means “not applicable” and “dc” means “don’t care.” 2. See “Test Conditions” on page 42 for output capacitive loading. I/O Specifications—Group 1 (Sheet 1 of 3) Notes: 1. PCI timings are for operation up to 66.66MHz. PCI output hold time requirement is 1ns for 66.66MHz and 2ns for 33.33MHz. In synchronous mode, timing is relative to SysClk. In asynchronous mode, timing is relative to PCIClk. 2. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 3. For PCI, I/O H is specified at 0.9OVDD and I/O L is specified at 0.1OVDD. For all other interfaces, I/O H is specified at 2.4 V and I/O L is specified at 0.4 V. Signal Input (ns) Output (ns) Output Current (mA) Clock Notes Setup Time (TIS min) Hold Time (TIH min) Valid Delay (TOV max) Hold Time (TOH min) I/O H (min) I/O L (min) PCI Interface PCIAD31:0 3 0 6 1 0.5 1.5 PCI Clock 1 PCIC3:0[BE3:0] 3 0 6 1 0.5 1.5 PCI Clock 1 PCIClk dc dc na na na na async PCIDevSel 3 0 6 1 0.5 1.5 PCI Clock 1 PCIFrame 3 0 6 1 0.5 1.5 PCI Clock 1 PCIGnt0[Req] PCIGnt1:5 na na na na 0.5 1.5 PCI Clock 1 PCIIDSel 3 0 6 1 na na PCI Clock 1 PCIINT[PerWE] na na dc dc 0.5 1.5 PCI Clock async PCIIRDY 3 0 6 1 0.5 1.5 PCI Clock 1 PCIParity 3 0 6 1 0.5 1.5 PCI Clock 1 PCIPErr 3 0 6 1 0.5 1.5 PCI Clock 1 PCIReq0[Gnt] PCIReq1:5 5 0 na na na na PCI Clock 1 PCIReset na na na na 0.5 1.5 PCI Clock PCISErr na na na na 0.5 1.5 PCI Clock PCIStop 3 0 6 1 0.5 1.5 PCI Clock 1 PCITRDY 3 0 6 1 0.5 1.5 PCI Clock 1 Ethernet Interface EMCMDClk na na settable 2 10.3 7.1 2, async EMCMDIO[PHYMDIO] 100 0 1 OPB clock period + 10ns 1 OPB clock period 10.3 7.1 EMCMDClk 2 EMCTxD3:0 na na 20 2 10.3 7.1 PHYTX 2 EMCTxEn na na 20 2 10.3 7.1 PHYTX 2 EMCTxErr na na 20 2 10.3 7.1 PHYTX 2 PHYCol 10.3 7.1 2, async PHYCrS 10.3 7.1 2, async PHYRxClk na na 2, async PHYRxD3:0 4 1 na na 10.3 7.1 PHYRX 2 PHYRxDV 4 1 na na 10.3 7.1 PHYRX 2 PHYRxErr 4 1 na na 10.3 7.1 PHYRX 2 PHYTxClk na na 2, async |
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