PPC440GP-3CC466C datasheet(50/83 Pages) AMCC

50 / 83 page

440GP – Power PC 440GP Embedded Processor

AMCC

Revision 1.07 – October 4, 2007

Data Sheet

EMCTxEn,

EMC0TxEn

MII: Transmit data enabled

RMII 0: Transmit data enabled

5V tolerant

3.3V LVTTL

EMCTxErr,

EMC1TxEn

MII: Transmit error:

RMII: Transmit data enabled

5V tolerant

3.3V LVTTL

External Slave Peripheral Interface

DMAAck0:3

Used by the PPC440GP to indicate that data transfers have

occurred.

5V tolerant

3.3V LVTTL

DMAReq0:3

Used by slave peripherals to indicate they are prepared to transfer

data.

5V tolerant

3.3V LVTTL

1, 5

EOT0:3/TC0:3

End Of Transfer/Terminal Count.

I/O

5V tolerant

3.3V LVTTL

1, 5

PerAddr00:31

Peripheral address bus used by PPC440GP when not in external

master mode, otherwise used by external master.

Note: PerAddr00 is the most significant bit (msb) on this bus.

I/O

5V tolerant

3.3V LVTTL

PerWBE0:3

External peripheral data bus byte enables.

I/O

5V tolerant

3.3V LVTTL

1, 2

PerBLast

Used by either the peripheral controller, DMA controller, or

external master to indicates the last transfer of a memory access.

I/O

5V tolerant

3.3V LVTTL

1, 4

PerCS0:7

External peripheral device select.

5V tolerant

3.3V LVTTL

PerData00:31

Peripheral data bus used by PPC440GP when not in external

master mode, otherwise used by external master.

Note: PerData00 is the most significant bit (msb) on this bus.

I/O

5V tolerant

3.3V LVTTL

PerOE

Used by either peripheral controller or DMA controller depending

upon the type of transfer involved. When the PPC440GP is the

bus master, it enables the selected device to drive the bus.

5V tolerant

3.3V LVTTL

PerPar0:3

External peripheral data bus byte parity.

I/O

5V tolerant

3.3V LVTTL

PerReady

Used by a peripheral slave to indicate it is ready to transfer data.

5V tolerant

3.3V LVTTL

PerR/W

Used by the PPC440GP when not in external master mode, as

output by either the peripheral controller or DMA controller

depending upon the type of transfer involved. High indicates a

read from memory, low indicates a write to memory.

Otherwise, it used by the external master as an input to indicate

the direction of transfer.

I/O

5V tolerant

3.3V LVTTL

1, 2

PerWE

Write Enable. Low when any of the four PerWBE0:3 signals are

low.

5V tolerant

3.3V LVTTL

Signal Functional Description (Sheet 3 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to 3.3V, 10kΩ to 5V)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to 3.3V)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PPC440GP-3CC466C Datasheet(PDF) 50 Page - Applied Micro Circuits Corporation

PPC440GP-3CC466C Datasheet(HTML) 50 Page - Applied Micro Circuits Corporation

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