SN54ACT574, SN74ACT574

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS537D – OCTOBER 1995 – REVISED NOVEMBER 2002

4

POST OFFICE BOX 655303

(unless otherwise noted) (see Figure 1)

TA = 25°C

SN54ACT574

SN74ACT574

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency

100

70

85

MHz

tw

Pulse duration, CLK high or low

3

5

4

ns

tsu

Setup time, data before CLK

↑

2.5

3.5

2.5

ns

th

Hold time, data after CLK

↑

1

2

1

ns

switching characteristics over recommended operating free-air temperature range,

PARAMETER

FROM

TO

TA = 25°C

SN54ACT574

SN74ACT574

UNIT

PARAMETER

(INPUT)

(OUTPUT)

MIN

TYP

MAX

MIN

MAX

MIN

MAX

UNIT

fmax

100

110

70

85

MHz

tPLH

CLK

Q

2.5

7

11

1.5

13.5

2

12

ns

tPHL

CLK

Q

2

6.5

10

1.5

12.5

1.5

11

ns

tPZH

OE

Q

2

6.4

9.5

1.5

11

1.5

10

ns

tPZL

OE

Q

2

6

9

1.5

11

1.5

10

ns

tPHZ

OE

Q

2

7

10.5

1.5

12

1.5

11.5

ns

tPLZ

OE

Q

2

5.5

8.5

1.5

10

1.5

9

ns

PARAMETER

TEST CONDITIONS

TYP

UNIT

Cpd

Power dissipation capacitance

CL = 50 pF,

f = 1 MHz

40

pF

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design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.