6

HV746

Pin Description

Pin #

Name

Function

1

VDD

Positive internal voltage supply (+9.0V).

2

VSS

Power supply return (0V).

3

PIN1

Input logic control of high voltage output P-FET of channel 1, Hi = ON, Low = OFF.

4

NIN1

Input logic control of high voltage output N-FET of channel 1, Hi = ON, Low = OFF.

5, 6, 7, 8

N/C

Not Connected

9

PIN2

Input logic control of high voltage output P-FET of channel 2, Hi = ON, Low = OFF.

10

NIN2

Input logic control of high voltage output N-FET of channel 2, Hi = ON, Low = OFF.

11

VSS

Power supply return (0V).

12

VDD

Positive internal voltage supply (+9.0V).

13

OTP

Over temperature protection output, open N-FET drain, active low if IC temperature >110°C.

14

MC1

Output current mode control pins, see Drive Mode Control Table.

15

MC0

16

VSUB

Substrate of the IC, All VSUB pins must connect to the most positive potential of the IC externally.

17

VPF

P-FET gate driver floating power supply, (V

18,19, 20

VPP

Positive high voltage power supply (+75V).

21, 22, 23

VNN

Negative high voltage power supply (-75V).

24

VNF

N-FET gate driver floating power supply, (V

25

VSUB

Substrate of the IC, all VSUB pins must connect to the most positive potential of the IC externally.

26

RGND

Bleed resistors common return ground.

27

TXN2

Output N-FET drain (open drain output) for channel 2.

28

29

TXP2

Output P-FET drain (open drain output) for channel 2.

30

31

TXN1

Output N-FET drain (open drain output) for channel 1.

32

33

TXP1

Output P-FET drain (open drain output) for channel 1.

34

35

RGND

Bleed resistors common return ground.

36

VSUB

Substrate of the IC, all VSUB pins must connect to the most positive potential of the IC externally.

37

VNF

N-FET gate driver floating power supply, (V

38, 39, 40

VNN

Negative high voltage power supply (-75V).

41, 42, 43

VPP

Positive high voltage power supply (+75V).

44

VPF

P-FET gate driver floating power supply, (V

45

VSUB

Substrate of the IC, all VSUB pins must connect to the most positive potential of the IC externally.

46

EN

Chip power enable Hi = ON, Low = OFF.

47

GREF

Logic low reference, logic ground (0V).

48

VLL

Logic Hi voltage reference input (+3.3V).

Thermal Pad

(VSUB)

Substrate bottom is internally connected to the central thermal pad on the bottom of package. It

must be connected to VSUB, the most positive potential of the IC externally.