SC1404 datasheet(10/25 Pages) SEMTECH

10 / 25 page

 2004 Semtech Corp.

www.semtech.com

SC1404

PRELIMINARY

POWER MANAGEMENT

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Current Sense (CSH, CSL)

Output current of each supply is sensed at the CSH and CSL pins.

Overcurrent is reached when the current sense voltage exceeds

55mV typical. On a cycle-by-cycle basis, a positive overcurrent

turns off the high-side driver and a negative overcurrent turns off

the low-side driver.

Oscillator

When the SYNC pin is high the oscillator runs at 300kHz; when

SYNC is low the frequency is 200kHz. The oscillator will synchronize

to the falling edge of a clock on the SYNC pin with a frequency

between 240kHz and 350kHz. In general, 200kHz operation

provides highest efficiency, while 300kHz allows for smaller output

ripple and/or smaller filter components.

Fault Protection

In addition to cycle-by-cycle current limit, the SC1404 provides

overtemperature, output overvoltage, and undervoltage

protection. Overtemperature protection will shut the device down

if die temperature exceeds 150

°C, with 10°C hysteresis.

If either SMPS output is more than 10% above its nominal value,

both SMPS are latched off and the low side mosfets are latched

on. To prevent the output from ringing below ground in a fault

condition, a 1A Schottky diode should be placed across each output.

Two different levels of undervoltage (UV) are detected. If the output

falls 9% below its nominal value, the RESET# output is pulled low.

If the output falls 25% below its nominal value, both SMPS are

latched off.

Both of the latched faults (OVP and UV) persist until SHDN or ON3

is toggled, or the V+ input is brought below 1V.

Shutdown and Operating Modes

Holding the SHDN pin low disables the SC1404, reducing the V+

input current to less than 10uA. When SHDN is high, the part

enters standby mode where the VL regulator and VREF are enabled.

Turning on either SMPS will put the SC1404 in run mode.

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Power up Controls and Soft Start

The user controls the SC1404 RESET# through the SEQ, ON3 and

ON5 pins, as shown in the Startup Sequence Chart. At startup,

RESET# is held low for 32K switching cycles, and then RESET# is

determined by the output voltages and the SEQ pin.

To prevent surge currents at startup, each SMPS has a counter

and DAC to incrementally raise the current limit (CSH-CSL voltage).

The current limit follows discrete steps of typically 25%, 40%, 60%,

80%, and 100%, each step lasting 128 clock cycles. To charge up

the output capacitors, inductor current at startup must exceed

load current. When the output voltage reaches it’s nominal value

the SMPS will reduce duty cycle, but the excess LI2 energy of the

inductor must flow into the load and output capacitors. If the

output capacitor is relatively small, the peak output voltage can

approach the overvoltage trip point. To prevent nuisance OVP at

startup, the inductance and capacitance must meet the following

criteria:

⋅

≤

MAX

NOM

MIN

MAX

MAX_OC is the maximum inductor current set by the current-limit

components, and V

O_NOM is the nominal output voltage.

12OUT Supply

The 12OUT linear regulator is capable of supplying 200mA. The

input voltage to the 12OUT regulator is generated by a secondary

winding on the 5V SMPS inductor.

A heavy load on the 12OUT regulator when the 5V SMPS operates

in PSAVE mode will cause VDD to sag, causing 12OUT to drop. If

12OUT output drops 0.8% from its nominal value, the 5V SMPS is

forced out of PSAVE mode and into PWM mode for several cycles.

This recharges the bulk input capacitor on VDD.

The 12OUT linear regulator has internal protection to prevent

damage under short circuit conditions. Overvoltage protection is

provided on the VDD input. If VDD rises above 19V, a 10mA shunt

load is applied to VDD to reduce the voltage. The overvoltage

threshold has 0.5V hysteresis.

SC1404 Datasheet(PDF) 10 Page - Semtech Corporation

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