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XIO2000A Datasheet(PDF) 25 Page - Texas Instruments |
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XIO2000A Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 155 page  Introduction 15 April 2007 SCPS155B Table 2−7. PCI Express Terminals SIGNAL GZZ/ ZZZ BALL # ZHH BALL # I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS DESCRIPTION PERST J17 H12 I LV CMOS VDD_33_ COMBIO − PCI Express reset input. The PERST signal identifies when the system power is stable and generates an internal power on reset. Note: The PERST input buffer has hysteresis. REF0_PCIE REF1_PCIE L16 L17 J14 J13 I/O BIAS − External resistor External reference resistor + and − terminals for setting TX driver current. An external resistor is connected between terminals L16 and L17. RXP RXN E17 E16 E14 E13 DI HS DIFF IN VSS − High-speed receive pair. RXP and RXN comprise the differential receive pair for the single PCI Express lane supported. TXP TXN H17 H16 G14 G13 DO HS DIFF OUT VDD_15 Series capacitors High-speed transmit pair. TXP and TXN comprise the differential transmit pair for the single PCI Express lane supported. WAKE M16 K14 O LV CMOS VDD_33_ COMBIO − Wake is an active low signal that is driven low to reactivate the PCI Express link hierarchy’s main power rails and reference clocks. Note: Since WAKE is an open-drain output buffer, a system side pullup resistor is required. Table 2−8. Clock Terminals SIGNAL GZZ/ZZZ BALL # ZHH BALL # I/O TYPE CELL TYPE CLAMP RAIL EXTERNAL PARTS DESCRIPTION REFCLK_SEL A16 A14 I LV CMOS VDD_33 Pullup or pulldown resistor Reference clock select. This terminal selects the reference clock input. 0 = 100-MHz differential common reference clock used. 1 = 125-MHz single-ended, reference clock used. REFCLK+ C17 C13 DI HS DIFF IN VDD_33 − Reference clock. REFCLK+ and REFCLK− comprise the differential input pair for the 100-MHz system reference clock. For a single-ended, 125-MHz system reference clock, use the REFCLK+ input. REFCLK− C16 C14 DI HS DIFF IN VDD_33 Capacitor to VSS for single-ended mode Reference clock. REFCLK+ and REFCLK− comprise the differential input pair for the 100-MHz system reference clock. For a single-ended, 125-MHz system reference clock, attach a capacitor from REFCLK− to VSS. CLK P03 L03 I PCI Bus VCCP − PCI clock input. This is the clock input to the PCI bus core. CLKOUT0 CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5 CLKOUT6 C08 B09 B10 A11 A12 A13 B14 D07 B08 A09 D10 B10 B11 A13 O PCI Bus VCCP − PCI clock outputs. These clock outputs are used to clock the PCI bus. If the bridge PCI bus clock outputs are used, then CLKOUT6 must be connected to the CLK input. |
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