EVK-SH3000USB datasheet(7/24 Pages) SEMTECH

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SH3000 MicroBuddy™

SYSTEM MANAGEMENT

V1.15 www.semtech.com

The watchdog timer is kept from timing out by

periodic reload of the time-out value, triggered by a write

of a code byte to the Watchdog Reload Register. As a

further safety measure, there are two different and

alternating code bytes that should be written to the same

Watchdog Reload Register. The code values are 0x5A

and 0xC3. The timer is reloaded after every write of a

single code byte.

The code byte should be written to the Watchdog

Reload Register, or reset is activated when the

watchdog timer expires. Also, reset is initiated

immediately if the value of the code byte is incorrect or

out of sequence. When the watchdog triggers the reset,

its duration is 12 ms.

Using two separate software routines, each to write

one of the code values, results in the highest level of

system security. These routines must execute in the

correct order. It is unlikely that runaway code could

manage this. In addition, this design makes it difficult for

the code to become stuck in a tight loop resetting the

watchdog.

Clock Management System

The SH3000 provides a flexible tool for creating and

managing clocks, a versatile and accurate “any

frequency” clock synthesizer (see Figure 4).

It is capable of generating any frequency in the

range of 62.5 kHz to 16.0 MHz, with worst-case

resolution of 0.0256% (256 ppm). The internal 32 kHz

clock can also be routed to the CLKOUT pin (and HF

oscillator stopped for energy savings).

The objectives, features, and behavior of the Clock

Management System are aimed towards the systems

that utilize a microcontroller, a microprocessor, a DSP or

an ASIC.

The SH3000 permits the automatic sensing of the

intentions of the host processor, an industry first. The

SH3000 shuts down its clock output when it senses that

the host processor issued a STOP instruction.

Subsequently, the SH3000 idles, consuming less than

10 µA. As soon as the host exits the STOP mode, the

SH3000 instantaneously starts to supply a stable clock

(<2µs wake-up).

A typical system, constructed with a ceramic

resonator or a crystal as the frequency determining

element, must wait at least several hundred

microseconds (for a resonator), or as much as 100 ms or

more (for a HF crystal), to re-start the oscillator. The

SH3000 allows the response to and service of an event

to finish with a speed previously unattainable for a

simple microprocessor. A system with a traditional clock

approach may be as much as 100x – 10,000x slower.

Clock Generator Operation

The frequency synthesizer in the SH3000 is

constructed from the 2:1 tunable 8.0 –16.0 MHz HF

oscillator followed by a programmable “power-of-two”

post-divider (see Figure 4).

The Clock Source selector and the programmable

post-scale divider allow instantaneous switching

between the 32 kHz internal clock and divided-down HF

oscillator output. There is no settling or instability when

the switch occurs.

This is a preferred method for clock control in

computing systems, when the large ratio between high

and low frequency of operations allows for

correspondingly large and instantaneous savings in

power consumption.

Post-scaler

(Divide by 1, 2, 4,

8, 16, 32, 64, 128)

Figure 4. Simplified HF Oscillator System

32.768 kHz

START/STOP

CLKOUT

CLKIN

Clock Buffer

and Glue

Logic

HF Digitally

Controlled

Oscillator

8-16 MHz

18-bit

DCO Code

Clock On

Force

DCO On

Clock Source

Spectrum

Spreading

Controls

Frequency Locked Loop

Logic

13-bit

Frequency

Set value

÷ 16 2048 Hz

8-bit Pseudo

Random Noise

Generator

FLL On

From / To

Serial I/O

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