CD74HC4024PWRE4 datasheet(6/15 Pages) TI

6 / 15 page

Output Transition

tTLH,tTHL CL = 50pF

4.5

Input Capacitance

CIN

CL =15pF

Power Dissipation Capacitance

(Notes 3, 4)

CPD

CL =15pF

NOTES:

3. CPD is used to determine the dynamic power consumption, per package.

4. PD =VCC

2 f

i + ∑ (CLVCC

2 fi/M) where: M = 21,22,23,24,25,26,27 f

i = Input Frequency, CL = Output Load Capacitance, VCC = Supply

Voltage.

Switching Speciﬁcations Input tr, tf = 6ns (Continued)

PARAMETER

SYMBOL

TEST

CONDITIONS

VCC

(V)

25oC

-40oC TO 85oC -55oC TO 125oC

UNITS

MIN

TYP

MAX

MIN

MAX

MIN

MAX

Test Circuits and Waveforms

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in

accordance with device truth table. For fMAX, input duty cycle = 50%.

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

CLOCK

90%

50%

10%

GND

VCC

trCL

tfCL

50%

tWL

tWH

10%

tWL + tWH =

fCL

CLOCK

2.7V

1.3V

0.3V

GND

trCL = 6ns

tfCL = 6ns

1.3V

tWL

tWH

0.3V

tWL + tWH =

fCL

tPHL

tPLH

tTHL

tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns

tf = 6ns

90%

tPHL

tPLH

tTHL

tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns

tf = 6ns

90%

CD54/74HC4024, CD54/74HCT4024

CD74HC4024PWRE4 Datasheet(PDF) 6 Page - Texas Instruments

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