SC4810EITSTRT datasheet(15/24 Pages) SEMTECH

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 2006 Semtech Corp.

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SC4810B/E

POWER MANAGEMENT

PCB Layout Guidelines

PCB layout is very critical, and the following should be

used to insure proper operation of the SC4810. High

switching currents are present in applications and their

effect on ground plane must be understood and

minimized.

1) The high power parts of the circuit should be placed

on a board first. A ground plane should be used. Isolated

or semi-isolated areas of the ground plane may be delib-

erately introduced to constrain ground currents to par-

ticular areas, for example the input capacitor and the

main switch FET ground.

2) The loop formed by the Input Capacitor(s) (Cin), the

main transformer and the main switch FET must be kept

as small as possible. This loop contains all the high fast

transient switching current. Connections should be as

wide and as short as possible to minimize loop induc-

tance. Minimizing this loop area will a) reduce EMI, b)

lower ground injection currents, resulting in electrically

“cleaner” grounds for the rest of the system and c) mini-

mize source ringing, resulting in more reliable gate switch-

ing signals.

3) The connection between FETs and the main trans-

former should be a wide trace or copper region. It should

be as short as practical. Since this connection has fast

voltage transitions, keeping this connection short will

minimize EMI.

4) The output capacitor(s) (Cout) should be located as

close to the load as possible. Fast transient load cur-

rents are supplied by Cout only. Connections between

Cout and the load must be short, wide copper areas to

minimize inductance and resistance.

5) A 0.1uF to 1uF ceramic capacitor should be directly

connected between VDD and PGND and a 1uF to 4.7uF

ceramic capacitor between VREF and PGND. The SC4810

is best placed over a quiet ground plane area. Avoid pulse

currents in the Cin and the main switch FET loop flowing

in this area. GND should be returned to the ground plane

close to the package and close to the ground side of

(one of) the VDD supply capacitor(s). Under no

circumstances should GND be returned to a ground inside

the Cin and the main switch FET loop. This can be

achieved by making a star connection between the quiet

GND planes that the SC4810 will be connected to and

the noisy high current GND planes connected to the FETs.

6) The feed back connection between the error ampli-

fier and the FB pin should be kept as short as possible,

and the GND connections should be to the quiet GND

used for the SC4810.

7) If an opto-coupler is used for isolation, quiet primary

and secondary ground planes should be used. The same

precautions should be followed for the primary GND plane

as mentioned in item 5. For the secondary GND plane,

the GND plane method mentioned in item 4 should be

followed.

8) All the noise sensitive components such as VDD by-

pass capacitor, RCT oscillator resistor/capacitor network,

DMAX resistive divider, VREF by pass capacitor, delay

setting resistors, current sensing circuitry and feedback

circuitry should be connected as close as possible to the

SC4810. The GND return should be connected to the

quiet SC4810 GND plane.

9) The connection from the OUT of the SC4810 should

be minimized to avoid any stray inductance. If the layout

can not be optimized due to constraints, a small Schottky

diode may be connected from the OUT pin to the ground

directly at the IC. This will clamp excessive negative volt-

ages at the IC.

10) If the SYNC function is not used, the SYNC pin should

be grounded at the SC4810 GND to avoid noise pick up.

Applications Information (Cont.)

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