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 2005 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1218

Applications Information (Cont.)

Typically, a 1uF/16V ceramic capacitor is used. In addi-

tion, a small resistor (one ohm) is recommended in be-

tween DRN pin of the SC1218 and the phase node. The

resistor is used to alleviate the stress of the SC1218, re-

sulting from the negative spike at the phase node, and

also to control the switching speed. A negative spike could

occur at the phase node during the top FET turn-off due to

parasitic inductance in the switching loop. The spike could

be minimized with a careful PCB layout. In the applica-

tions with TO-220 package FETs, it is suggested to use a

clamping diode on the DRN pin to mitigate the impact of

the excessive phase node negative spikes.

For VIN pin of the SC1218, it is recommended to use a

1uF/16V ceramic capacitor for decoupling.

Driv

Driv

Driv

Driv

Driver Dissipation and Junction T

er Dissipation and Junction T

er Dissipation and Junction T

er Dissipation and Junction T

er Dissipation and Junction Tem

em

em

em

emperature

perature

perature

perature

perature

The driver power dissipation is a function of chip quies-

cent current I

age V

IN

SW

TOTAL

Q

D

V

F

Q

I

P

⋅

⋅

+

=

)

(

where Q

bottom-side FETs. The power dissipation vs total gate

charge at the given switching frequency is plotted in Fig.11.

The driver junction temperature can be calculated based

on the juntion to case thermal resistance and Printed Cir-

cuit Board (PCB) temperature.

LA

LA

LA

LA

LAYYYYYOUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

OUT GUIDELINES

The switching regulator is a high di/dt and dv/dt power

circuit. PCB layout is critical. A good layout can achieve

optimum circuit performance with minimized component

stress, resulting in better system reliability. For a multi-

phase voltage regulator, the SC1218 driver, FETs, induc-

tor, and supply decoupling capacitors in each phase have

to be considered as a unit. For the SC1218 driver, the

following guidelines are typically recommended during PCB

layout:

a) Place the SC1218 close to the FETs for shortest

gate drive traces and ground return paths;

b) Connect decoupling capacitor as close as possible

to the VIN pin and the PGND pin. The trace length of

the capacitor on the VIN pin should be no more than

0.2” (5mm); and

c) Locate the bootstrap capacitor close to the SC1218.

The typical layout examples of SC1218 based on above

guidelines are shown in Fig.12 and Fig.13.

0

200

400

600

800

1000

40

60

80

100

120

TOTAL GATE CHARGE (nC)

Fsw=200kHz

Fsw=400kHz

Fsw=600kHz

0

200

400

600

800

1000

40

60

80

100

120

TOTAL GATE CHARGE (nC)

Fsw=200kHz

Fsw=200kHz

Fsw=400kHz

Fsw=400kHz

Fsw=600kHz

Fsw=600kHz

Fig. 11. Power dissipation.

VIN

VIN

To top FET

To bottom FET

To phase node

PWM

R

C

C

To top FET

To bottom FET

PWM

VIN

VIN

To top FET

To bottom FET

To phase node

PWM

R

C

C

To top FET

To bottom FET

PWM

Fig. 12. Component placement for SOIC-8

EN

To Bottom FET

To Top FET

VIN

To Phase Node

EN

To Bottom FET

To Top FET

VIN

To Phase Node

Fig. 13. Component placement for MLPQ-8.