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 2005 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC605

Suggested Layout

The following layout is suggested for a two layer design with

one component side. The capacitors C and C2 are the

bucket capacitors and each of these capacitors conducts

the full load current of up to 700mA pulsed on for one half

clock cycle per capacitor. C3 is the output decoupling ca-

pacitor, placed near the SC605. C is the input decoupling

capacitor, placed near the SC605. Multiple vias should be

used whenever it is necessary to change layers on nets

connecting to pins VIN, VOUT, GND, C1-, C1+, C2-, C2+.

Resistor R1 is routed with a very low resistance connection

between ISET and GND pin 3. The sense trace between

pin 7 and R1 is connected to R1 at the terminal pad for

the most accurate sensing possible.

The bottom copper layer is primarily a ground plane provid-

ing a return path between the ground vias at R1 and the

ground vias connecting pin 3 to the ground plane.

The SC605’s center thermal pad is tied to the ground plane

through a heat spreading copper shape with multiple vias.

There are 0 vias shown in this layout connecting the ther-

mal pad and pin 3 together to the ground plane. All 0 vias

help spread heat and conduct ground current. Note that

the thermal pad does not conduct current. Pin 3 conducts

the full ground current.

Four signal traces routed on the bottom layer are CTRL1,

CTRL0, FLASH and ISET. These traces are routed horizon-

tally on the bottom layer. Carefully route these traces so

they do no block the ground path from R1 to the ground

pin 3.

TopCopper

BottomCopper