PI7C8152AMA datasheet(7/90 Pages) PERICOM

7 / 90 page

PI7C8152A & PI7C8152B

2-PORT PCI-TO-PCI BRIDGE

ADVANCE INFORMATION

Page 7 of 90

October 16, 2003 – Revision 1.11

12.1.5

REVISION ID REGISTER – OFFSET 08h ...................................................................... 70

12.1.6

CLASS CODE REGISTER – OFFSET 08h....................................................................... 70

12.1.7

CACHE LINE SIZE REGISTER – OFFSET 0Ch ............................................................ 70

12.1.8

PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch ........................................... 70

12.1.9

HEADER TYPE REGISTER – OFFSET 0Ch................................................................... 70

12.1.10

PRIMARY BUS NUMBER REGISTSER – OFFSET 18h............................................ 71

12.1.11

SECONDARY BUS NUMBER REGISTER – OFFSET 18h ........................................ 71

12.1.12

SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h.................................... 71

12.1.13

SECONDARY LATENCY TIMER REGISTER – OFFSET 18h .................................. 71

12.1.14

I/O BASE ADDRESS REGISTER – OFFSET 1Ch ...................................................... 71

12.1.15

I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch ..................................................... 72

12.1.16

SECONDARY STATUS REGISTER – OFFSET 1Ch................................................... 72

12.1.17

MEMORY BASE ADDRESS REGISTER – OFFSET 20h ........................................... 73

12.1.18

MEMORY LIMIT ADDRESS REGISTER – OFFSET 20h.......................................... 73

12.1.19

PEFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h ............. 73

12.1.20

PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER – OFFSET 24h ......... 73

12.1.21

PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER –

OFFSET 28h ....................................................................................................................................... 74

12.1.22

PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER –

OFFSET 2Ch....................................................................................................................................... 74

12.1.23

I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .......................... 74

12.1.24

I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h......................... 74

12.1.25

ECP POINTER REGISTER – OFFSET 34h................................................................. 74

12.1.26

INTERRUPT PIN REGISTER – OFFSET 3Ch............................................................ 75

12.1.27

BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................... 75

12.1.28

DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h.................................. 76

12.1.29

ARBITER CONTROL REGISTER – OFFSET 40h...................................................... 78

12.1.30

EXTENDED CHIP CONTROL REGISTER – OFFSET 48h....................................... 78

12.1.31

SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET

4Ch

.......................................................................................................................................... 79

12.1.32

P_SERR_L EVENT DISABLE REGISTER – OFFSET 64h........................................ 79

12.1.33

SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h ................................. 80

12.1.34

P_SERR_L STATUS REGISTER – OFFSET 68h ........................................................ 81

12.1.35

PORT OPTION REGISTER – OFFSET 74h ................................................................ 81

12.1.36

PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h ..................................... 83

12.1.37

SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h ............................... 84

12.1.38

CAPABILITY ID REGISTER – OFFSET DCh............................................................. 84

12.1.39

NEXT ITEM POINTER REGISTER – OFFSET DCh ................................................. 84

12.1.40

POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh ................. 84

12.1.41

POWER MANAGEMENT DATA REGISTER – OFFSET E0h................................... 84

12.1.42

PPB SUPPORT EXTENSIONS REGISER – OFFSET E0h ........................................ 85

BRIDGE BEHAVIOR.................................................................................................................... 85

13.1

BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES................................................................ 85

13.2

ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER)..................................... 86

13.2.1

MASTER ABORT................................................................................................................ 86

13.2.2

PARITY AND ERROR REPORTING ................................................................................ 86

13.2.3

REPORTING PARITY ERRORS ....................................................................................... 86

13.2.4

SECONDARY IDSEL MAPPING ...................................................................................... 86

ELECTRICAL AND TIMING SPECIFICATIONS................................................................... 87

14.1

MAXIMUM RATINGS ............................................................................................................... 87

14.2

DC SPECIFICATIONS ................................................................................................................ 87

14.3

AC SPECIFICATIONS ................................................................................................................ 87

PI7C8152AMA Datasheet(PDF) 7 Page - Pericom Semiconductor Corporation

PI7C8152AMA Datasheet(HTML) 7 Page - Pericom Semiconductor Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Datasheet Download

Link URL