L6566B datasheet(36/51 Pages) STMICROELECTRONICS

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Application information

L6566B

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Figure 23. OVP function: timing diagram

The value of RZ1 will be such that the current sourced by the ZCD pin be within the rated

capability of the internal clamp:

Equation 14

where Vinmax is the maximum dc input voltage and Ns the turn number of the primary

winding. See Section 5.2: Zero current detection and triggering block; oscillator block on

page 21

for additional details.

To reduce sensitivity to noise and prevent the latch from being erroneously activated, first

the OVP comparator is active only for a small time window (typically, 0.5 µs) starting 2 µs

after MOSFET’s turn-off, to reject the voltage spike associated to the positive-going edges

of the voltage across the auxiliary winding Vaux; second, to stop the L6566B the OVP

comparator must be triggered for four consecutive switching cycles. A counter, which is

reset every time the OVP comparator is not triggered in one switching cycle, is provided to

this purpose.

Figure 22 on page 35

shows the internal block diagram, while the timing diagrams in

Figure 23

illustrate the operation.

Note:

To use the OVP function effectively, i.e. to ensure that the OVP comparator will be always

interrogated during MOSFET’s OFF-time, the duty cycle D under open-loop conditions must

fulfill the following inequality:

(pin 4)

Vaux

STROBE

COUNTER

RESET

COUNTER

STATUS

ZCD

(pin 11)

2 µs

0.5µs

OVP

FAULT

→11 →22 →00 →11 →22 →33 →4

NORMAL OPERATION

TEMPORARY DISTURBANCE

FEEDBACK LOOP FAILURE

COUT

max

Vin

Naux

−

⋅

≥

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