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Board Traces

VIA ConnectedtoLVPlane

VIA Connectedto5VPlane

VIA ConnectedtoGNDPlane

GND

5Vout

High-speedlines

Controllines

1

38

20

TPD12S521

HDMICoreChip

HDMI

Connector

19

CLK–

GND

CLK+

D0–

GND

D0+

D1–

GND

D1+

D2–

GND

D2+

HTDT

5OUT

GND

D_DT

D_CK

NC

CE_R

TPD12S521

SINGLE-CHIP HDMI TRANSMITTER PORT PROTECTION AND INTERFACE DEVICE

SLVS639 – OCTOBER 2007

A.

External bypass capacitors and resistor components not included

Figure 1. Board Layout for HDMI Transmitter Using TPD12S521DBTR

PIN DESCRIPTION

PIN NO.

NAME

DESCRIPTION

4, 35

TMDS_D2+

6, 33

TMDS_D2–

7, 32

TMDS_D1+

9, 30

TMDS_D1–

10, 29

TMDS_D0+

12, 27

TMDS_D0–

13, 26

TMDS_CK+

15, 24

TMDS_CK–

16

CE_REMOTE_IN

LV_SUPPLY referenced logic level in

23

CE_REMOTE_OUT

5V_SUPPLY referenced logic level out, plus 3.5-pF ESD

17

DDC_CLK_IN

LV_SUPPLY referenced logic level in

22

DDC_CLK_OUT

5V_SUPPLY referenced logic level out, plus 3.5-pF ESD

18

DDC_DAT_IN

LV_SUPPLY referenced logic level in

21

DDC_DAT_OUT

5V_SUPPLY referenced logic level out, plus 3.5-pF ESD

19

HOTPLUG_DET_IN

LV_SUPPLY referenced logic level in

20

HOTPLUG_DET_OUT

5V_SUPPLY referenced logic level out, plus 3.5-pF ESD

2

LV_SUPPLY

Bias for CE/DDC/HOTPLUG level shifters

1

5V_SUPPLY

Current source for 5V_OUT

55-mA minimum overcurrent protected 5-V output. This output must be

38

5V_OUT

bypassed with a 0.1-

μF ceramic capacitor.

37

ESD_BYP

ESD bypass. This pin must be connected to a 0.1-

μF ceramic capacitor.

3, 5, 8, 11, 14,

GND/TMDS_GND

GND reference

25, 28, 31, 34, 36

(1)

These two pins must be connected together inline on the PCB.

(2)

These two pins must be connected together inline on the PCB.

Copyright © 2007, Texas Instruments Incorporated

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3

Product Folder Link(s): TPD12S521