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ML145503EP Datasheet(PDF) 7 Page - LANSDALE Semiconductor Inc. |
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ML145503EP Datasheet(HTML) 7 Page - LANSDALE Semiconductor Inc. |
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7 / 26 page  ML145502, ML145503, ML145505 LANSDALE Semiconductor, Inc. MODE CONTROL LOGIC (VSS to VDD = 4.75 V to 12.6 V, TA = – 40 to + 85°C) Characteristic Min Typ Max Unit VLS Voltage for TTL Mode (TTL Logic Levels Referenced to VLS) VSS — VDD – 4.0 V VLS Voltage for CMOS Mode (CMOS Logic Levels of VSS to VDD) VDD – 0.5 — VDD V Mu/A Select Voltage Mu–Law Mode Sign Magnitude Mode A–Law Mode VDD – 0.5 VAG – 0.5 VSS — — — VDD VAG + 0.5 VSS + 0.5 V RSI Voltage for Reference Select Input (ML145502) 3.78 V Mode 2.5 V Mode 3.15 V Mode VDD – 0.5 VAG – 0.5 VSS — — — VDD VAG + 0.5 VSS + 0.5 V Vref Voltage for Internal or External Reference (ML145502 Only) Internal Reference Mode External Reference Mode VSS VAG + 0.5 — — VSS + 0.5 VDD – 1.0 V Analog Test Mode Frequency, MS = CCI (ML145502 Only) See Pin Description; Test Modes — 128 — kHz SWITCHING CHARACTERISTICS (VSS to VDD = 9.5 V to 12.6 V, TA = – 40 to + 85°C, CL = 150 pF, CMOS or TTL Mode) Characteristic Symbol Min Typ Max Unit Output Rise Time TDD Output Fall Time tTLH tTHL — — 30 30 80 80 ns Input Rise Time TDE, TDC, RCE, RDC, DC, MSI, CCI Input Fall Time tTLH tTHL — — — — 4 4 µs Pulse Width TDE Low, TDC, RCE, RDC, DC, MSI, CCI tw 100 — — ns DCLK Pulse Frequency (ML145502/05 Only) TDC, RDC, DC fCL 64 — 4096 kHz CCI Clock Pulse Frequency (MSI = 8 kHz) CCI is internally tied to TDC on the ML145503, therefore, the transmit data clock must be one of these frequencies. This pin will accept one of these discrete clock frequencies and will compensate to produce internal sequencing. fCL1 fCL2 fCL3 fCL4 fCL5 — — — — — 128 1536 1544 2048 2560 — — — — — kHz Propagation Delay Time TDE Rising to TDD Low Impedance TTL CMOS TDE Falling to TDD High Impedance TTL CMOS TDC Rising Edge to TDD Data, During TDE High TTL CMOS TDE Rising Edge to TDD Data, During TDC High TTL CMOS tP1 tP2 tP3 tP4 — — — — — — — — 90 90 — — 90 90 90 90 180 150 55 40 180 150 180 150 ns TDC Falling Edge to TDE Rising Edge Setup Time tsu1 20 — — ns TDE Rising Edge to TDC Falling Edge Setup Time tsu2 100 — — ns TDE Falling Edge to TDC Rising Edge to Preserve the Next TDD Data tsu8 20 — — ns RDC Falling Edge to RCE Rising Edge Setup Time tsu3 20 — — ns RCE Rising Edge to RDC Falling Edge Setup Time tsu4 100 — — ns RDD Valid to RDC Falling Edge Setup Time tsu5 60 — — ns CCI Falling Edge to MSI Rising Edge Setup Time tsu6 20 — — ns MSI Rising Edge to CCI Falling Edge Setup Time tsu7 100 — — ns RDD Hold Time from RDC Falling Edge th 100 — — ns TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI Input Capacitance — — 10 pF TDE,TDC, RCE, RDC, RDD, DC, MSI, CCI Input Current — ± 0.01 ± 10 µA TDD Capacitance During High Impedance (TDE Low) — 12 15 pF TDD Input Current During High Impedance (TDE Low) — ± 0.1 ± 10.0 µA www.lansdale.com Page 7 of 26 Issue A |
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