DATA SHEET

www.onsemi.com

 Semiconductor Components Industries, LLC, 2019

August, 2024 − Rev. 12

1

Publication Order Number:

XGS5M−PD/D

XGS 5000, XGS 3000 and

XGS 2000 Global Shutter

CMOS Image Sensors

XGS Family

Description

The XGS CMOS image sensor family provides high performance

global shutter image capture. The family comes in different

resolutions in a single package: 2, 3 and 5 MP with up to 2/3−inch

optical format. The 16 mm x 16 mm package makes the XGS family

particularly suited for integration in 29 mm x 29 mm camera formats.

The high speed, 12−bit output maximally leverages interfaces such as

USB 3.2, Thunderbolt

t 2 and 10 GigE.

Image data is read out through a column ADC architecture and then

transferred over a HiSPi interface. On−chip logic, programmable via

the serial interface, generates internal timing for integration and

readout control. Up to three register configurations can be

programmed and sequentially enabled (frame by frame) using a single

command over the control interface.

Table 1. KEY PERFORMANCE PARAMETERS

Parameter

Typical Value

Optical Format

XGS 5000

2/3−inch (10.6 mm Diagonal)

XGS 3000

1/2−inch (8.2 mm Diagonal)

XGS 2000

1/.2.2−inch (7.3 mm Diagonal)

Active Pixels

XGS 5000

2592 (H) x 2048 (V)

XGS 3000

2048 (H) x 1536 (V)

XGS 2000

1920 (H) x 1200 (V)

Pixel Size

3.2 mm

Color Filter Array

Monochrome, Bayer

Shutter Type

Global Shutter

Input Clock

32.4 MHz

Output Interface

HiSPi (16 Lanes − 777.6 Mbps/lane)

Frame Rate (12−bit)

16 Lanes (−X4)

XGS 5000

132

XGS 3000

175

XGS 2000

220

4 Lanes (−X5)

XGS 5000

43

Read Noise

4 e− (1x), 1.9 e− (4x)

SNRMAX

40 dB

Dynamic Range

68 dB

Supply Voltages

1.2 V, 2.8 V, 3 V (0.4 V, 1.8 V Optional)

Power Consumption

0.75 W

Operating Temp.

−40C to 85C (Junction)

Package

163−pin iLGA (Inspectable Land Grid Array)

Features

 On−chip 12−bit Column ADCs

 10−bit Mode with Increased Frame Rate of

148 fps (16−lane) at Full Resolution

 Companding & 10−Bit Mode at 100 fps

(8−lane) and 50 fps (8−lane)

 Dual Gain Mode with 74.5 dB Dynamic

Range (TJ = 40C) at Half Frame Rate

 Data Interface: 16−lane HiSPi

(Scalable Low−Voltage Signaling)

 Configurable Number of HiSPi Lanes:

16, 12, 8 or 4 Lanes

 Two−Wire (I2C) and Four−Wire (SPI)

Serial Interface

 Triggered Integration and Readout Control

 Programmable Control for up to 8 Regions

of Interest (ROI)

 Context Switching

 These Devices are Pb−Free, Halogen

Free/BFR Free and are RoHS Compliant

Applications

 Machine Vision

 Security

 Intelligent Transportation Systems (ITS)

 Broadcasting

 Medical

 Scientific

See detailed ordering and shipping information on page 2

of this data sheet.

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