MSM8128 datasheet(3/10 Pages) MOSAIC

3 / 10 page

MSM8128 - 70/85/10/12

Issue 4.5 : April 2001

Operating Modes

The table below shows the logic inputs required to control the MSM8128 SRAM.

Mode

CS1

CS2

CC Current

I/O Pin

Reference Cycle

Not Selected

SB1,ISB2

High Z

Power Down

Not Selected

SB,ISB1

High Z

Power Down

Output Disable

High Z

Read

OUT

Read Cycle

Write

Write Cycle

1 = V

IH,0 = VIL,

X = Don't Care

Low V

cc Data Retention Characteristics - L Version Only (TA=-55°C to +125

oC)

Parameter

Symbol Test Condition

min

typ

max

Unit

CC for Data Retention

CS1

≥≥≥≥≥

CC-0.2V, CS2 ≥

≥≥≥≥V

CC-0.2V or

≤≤≤≤≤CS2≤≤≤≤≤ 0.2V. V

IN≥

≥≥≥≥0V

2.0

Data Retention Current

CCDR

CC=3.0V,VIN ≥

≥≥≥≥0V, CS1≥≥≥≥≥V

CC-0.2V,

CS2

≥≥≥≥≥V

CC-0.2V or 0V ≤

≤≤≤≤ CS2 ≤≤≤≤≤ 0.2V.

660

µA

Chip Deselect to Data Retention

CDR

See Retention Waveform

Operation Recovery Time

See Retention Waveform

Notes (1) CS2 controls address buffer, WE buffer, CS1 buffer and OE buffer. If CS2 controls data retention mode,

Vin levels (WE,OE,CS1,I/O) can be in the high impedance state. If CS1 controls Data Retention mode,

CS2 must be

≥≥≥≥≥V

CC - 0.2V or 0V ≤

≤≤≤≤ CS2≤≤≤≤≤ 0.2V. The other input levels (address, WE,OE,I/O) can be in the

high impedance state.

AC Test Conditions

Output Load

* Input pulse levels: 0V to 3.0V

* Input rise and fall times: 5ns

* Input and Output timing reference levels: 1.5V

* Output load: See Load Diagram

* V

cc=5V±10%

166

30pF

I/O Pin

1.76V

Ω

MSM8128 Datasheet(PDF) 3 Page - MOSAIC

MSM8128 Datasheet(HTML) 3 Page - MOSAIC

Html Pages

1 2 3 4 5 6 7 8 9 10

Datasheet Download

Link URL