STE2004S datasheet(69/79 Pages) STMICROELECTRONICS

69 / 79 page

STE2004S

Electrical characteristics

69/79

Serial interface (

Figure 75)

FSCLK

Clock frequency

VDD1 = 1.7V;

MHz

TCYC

Clock cycle SCLK

125

TPWH1

SCLK pulse width HIGH

TPWL1

SCLK pulse width LOW

TS2

CS setup time

VDD1 = 1.7V

TH2

CS hold time

VDD1 = 1.7V

TPWH2

CS minimum high time

VDD1 = 1.7V

TS3

SD/C setup time

TH3

SD/C hold time

TS4

SDIN setup time

TH4

SDIN hold time

TS5

SDOUT access time

TH5

SDOUT disable time vs.

SCLK

020

TH6

SDOUT disable time vs.

020

For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated

Trise and Tfall (30%-70%) -10ns

CVLCD is the filtering capacitor on VLCD

All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and

VIH with an input voltage swing of VSS to VDD

Cb is the capacitive load for each bus line.

Table 28. AC operation

Symbol

Parameter

Test condition

Min.

Typ.

Max.

Unit

frame

osc

960

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STE2004S Datasheet(PDF) 69 Page - STMicroelectronics

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