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IRISMPS1

Circuit Description

The IRISMPS2 refererence design is a complete tested power supply circuit. It is designed for a 36-72V

DC line input and will provide a 5V, 5A full load DC output.

The design uses a flyback converter topology, with an IRIS4007K as the main switch and control device.

The initial startup current for the IRIS4007K is provided by a dropper resistor from the DC bus. Once the circuit

is started the Vcc power for the IRIS4007K comes from the bias winding of the main transformer. The primary

current control circuit consists of a current sensing resistor which feeds a voltage proportional to the trans-

former primary current into the feedback (FB) pin of the IRIS4007K. The secondary voltage control loop uses

a zener diode as the reference and an optocoupler to feedback the information across the transformer

isolation boundary back to the control circuit of the IRIS4007K.

Test Circuit Set-up

The circuit is designed for a 36-72V DC line input. To effectively test and evaluate this circuit it ios

recommended that a DC power supply with a 100V range is used that is capable of supplying 5A. The DC

input power is applied to the pins at P1(+) and P4(gnd) marked on the board.

For the output the best load to use is an electronic load which will allow easy changes in the output load,

e.g. something like a Chroma 63102. Another simple alternative is to use a High power resistor for the load.

Circuit Operation

The front end of the circuit consists of an EMI Filter. At power up the DC voltage is applied to the top of the

transformer, and the top of resistor R3. R3 allows about 450uA of quiescent current to flow which charges the

Vcc capacitor C9. When the voltage at the Vcc pin of the IRIS4007K reaches the positive undervoltage lockout

threshold (V

is applied across the transformer primary winding, the FET and the current sense resistor R10. The current

through the transformer primary, the FET and the current sense resistors will start to ramp up. the rate of the

ramp is dependent on the DC bus voltage . The current ramps until the voltage across R10 reaches the Vth1

of the IRIS4007K (0.73V typ). During this time there is no current flowing in either the bias winding or the

output winding, because this is blocked by the diodes D1 and D4 respectively.

At the point when the voltage across R10 reaches Vth1this activates a comparator in the IRIS4007K and

the internal FET is switched off. Now the energy stored in the transformer causes the voltage at the Drain

connected end of the transformer to rise, and as a result the voltage at the bias winding and the output winding

changes from negative to positive. The output rectifiers now conduct and the energy is transferred to the

output and the bias winding. If there is a fixed full current load on the output it will take a number of cycles for

the output voltage to rise to the required level, and also it will take a few cycles for the bias winding to begin

supplying power to the Vcc pin of the IRIS4007K. Until this happens, C9 holds the voltage above the

undervoltage lockout level (Vccuv-) to make sure the circuit does not drop out. During this time the circuit

cannot create enough voltage signal through the delay circuit to activate the quasi-resonant operation, so the

circuit operates with a fixed off time of 50us (this is the pulse raio control mode or PRC mode).

Once the the output capacitors C5/C6/C13 and the Vcc capacitor C6 are fully charged, the complete

quasi-resonant signal is passed through the delay circuit D5/R7/D6 to the feedback (FB) pin. This will give a

voltage above the Vth2 threshold of the IRIS4007K, and this activates the quasi-resonant operation, holding

the internal FET off until all the energy is transferred from the primary side of the transformer to the secondary

and bias outputs. When all the energy is transferred, the quasi-resonant signal at the FB pin will start to fall

until it can no longer supply the 1.35mA required by the IRIS4007K internal latch, and the FET is turned back