TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice.

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Issue 1.0.4

2018-01-25

TEWS TECHNOLOGIES GmbH

Am Bahnhof 7

25469 Halstenbek, Germany

Phone: +49 (0) 4101 4058 0

Fax: +49 (0) 4101 4058 19

e-mail: info@tews.com

www.tews.com

The Embedded I/O Company

TEWS offers a well-documented basic FPGA Example

Application design. It includes an .ucf file with all

necessary pin assignments and basic timing constraints.

The example design covers the main functionalities of the

TXMC635.

It implements local bus interface to local bridge device,

register mapping, DDR3 memory access and basic I/O. It

comes as a Xilinx ISE project with source code and as a

ready-to-download bit stream.

Technical Information

 Form Factor: Standard single width XMC

 Board size: 149 mm x 74 mm

 PCI Express (Base Specification 1.1) compliant

interface conforming to ANSI/VITA 42.3-2006

 IPMI resource: FRU hardware definition information

stored in on-board EEPROM

 TXMC635-10R Xilinx XC6SLX45T-2 Spartan6 FPGA

 TXMC635-20R Xilinx XC6SLX100T-2 Spartan6 FPGA

 Serial Flash for FPGA Configuration

 FPGA clock options:

 Local clock generator as source for the FPGA

internal PLL

 1 DDR3 SDRAM bank, 64M x 16 (128 MB)

 Front I/O lines

 48 TTL I/O

TTL signaling voltage (maximum current: +/-32mA)

direction individually programmable

 8 channels single-ended 16 bit analog output

 Programmable output voltage: ±10V,

±10.2564V or ±10.5263V

 Conversion time: typ.10µs

 Factory calibration

 32 single ended or 16 differential analog inputs

 16 bit resolution

 Conversion time: 1.1µs

 User programmable input voltage range

 Factory calibration

 Back I/O lines

 64 single ended or 32 differential back I/O lines on

rear connector P14.

 3 FPGA Multi-Gigabit-Transceiver on rear

connector P16

 Operating temperature -40°C to +85°C

 MTBF (MIL-HDBK217F/FN2 GB 20°C): tbd.