TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice.

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Issue 1.0.3

2018-01-25

TEWS TECHNOLOGIES GmbH

Am Bahnhof 7

25469 Halstenbek, Germany

Phone: +49 (0) 4101 4058 0

Fax: +49 (0) 4101 4058 19

e-mail: info@tews.com

www.tews.com

The Embedded I/O Company

Technical Information

 Form Factor: Standard single-width XMC module

conforming to ANSI/VITA 42.0-2008

 Board size: 149 mm x 74 mm

 PCI Express (Base Specification 1.1) compliant

interface conforming to ANSI/VITA 42.3-2006

 IPMI resource: FRU hardware definition information

stored in on-board EEPROM

 TXMC633-1xR: Xilinx XC6SLX45T-2 Spartan6 FPGA

configured by serial Flash

TXMC633-2xR: Xilinx XC6SLX100T-2 Spartan6

FPGA configured by serial Flash

 FPGA clock options:

 Local clock generator as source for the FPGA

internal PLL

1 DDR3 SDRAM bank, 64M x 16 (128 MB)

 32 Mbit SPI-EEPROM for User Data and FPGA

configuration

 Front I/O lines

64 TTL I/O, or 32 differential I/O or 32 TTL I/O

and 16 differential I/O

 TTL compatible signaling voltage, EIA-422/-485

signaling level

or M-LVDS Standard (TIA/EIA-899)

 direction individually programmable

 Back I/O lines

64 FPGA I/Os on P14 and 3 FPGA Multi-Gigabit-

Transceiver on P16

 P14 with 64 single ended LVCMOS33 or 32

differential LVDS33 depends on Spartan6

Configuration

 I/O access:

 64 I/O lines on HD68 front connector

 64 I/O lines on P14 Mezzanine connector

 3 MGT RxTx lines on P16 Mezzanine connector

 Operating temperature -40°C to +85°C

 MTBF (MIL-HDBK217F/FN2 GB 20°C): 320000 h

TXMC633 Block Diagram