PCA9535CD datasheet(14/32 Pages) NXP

14 / 32 page

PCA9535_PCA9535C_3

Product data sheet

Rev. 03 — 4 October 2007

14 of 32

NXP Semiconductors

PCA9535; PCA9535C

16-bit I2C-bus and SMBus, low power I/O port with interrupt

6.5.3 Interrupt output

The open-drain interrupt output is activated when one of the port pins change state and

the pin is conﬁgured as an input. The interrupt is deactivated when the input returns to its

previous state or the Input Port register is read (see Figure 11). A pin conﬁgured as an

output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt

caused by Port 0 will not be cleared by a read of Port 1 or the other way around.

Remark: Changing an I/O from an output to an input may cause a false interrupt to occur

if the state of the pin does not match the contents of the Input Port register.

Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

7.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 13).

7.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is deﬁned as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP

condition (P) (see Figure 14.)

Fig 13. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig 14. Deﬁnition of START and STOP conditions

mba608

SDA

SCL

STOP condition

SDA

SCL

START condition

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