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TMP93CS44 Datasheet(PDF) 151 Page - Toshiba Semiconductor |
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TMP93CS44 Datasheet(HTML) 151 Page - Toshiba Semiconductor |
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151 / 224 page ![]() TMP93CS44/S45 2004-02-10 93CS44-149 3.10.4 I 2C Bus Mode Control The following registers are used for control and operation status monitoring when using the serial bus interface (SBI) in the I2C bus mode. Serial Bus Interface Control Register 1 7 6 5 4 3 2 1 0 Bit symbol BC2 BC1 BC0 ACK SCK2 SCK1 SCK0 SBICR1 (004BH) Read/Write W R/W W After reset 0 0 0 0 0 0 0 Prohibit read-modify- write Function Number of transferred bits (Note 1) Acknowledge mode specification Serial clock selection (Note 2) Note 1: Set <BC2:0> to “000” before switching to a clock synchronous 8-bit SIO mode. Note 2: Refer to sentence of 3.10.4 (3) “Serial clock”. Note 3: This I 2C bus circuit does not support high-speed mode. It supports standard mode only. Figure 3.10.3 Register for I 2C Bus Mode (1/4) Serial clock selection 000 N = 4 − kHz 001 N = 5 − kHz 010 N = 6 − kHz 011 N = 7 74.6 kHz 100 N = 8 38.2 kHz 101 N = 9 19.3 kHz 110 N = 10 9.71 kHz System clock: fc Clock gear: fc/1 fc = 20 MHz (Output on SCL pin) 111 (Reserved) Acknowledge mode specification 0 Not generate clock pulse for acknowledge signal 1 Generate clock pulse for acknowledge signal Number of transferred bits <ACK> = 0 <ACK> = 1 <BC2:0> Number of Clock Bits Number of Clock Bits 000 8 8 9 8 001 1 1 2 1 010 2 2 3 2 011 3 3 4 3 100 4 4 5 4 101 5 5 6 5 110 6 6 7 6 111 7 7 8 7 |
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