TMP93CS44 datasheet(156/224 Pages) TOSHIBA

156 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-154

2. Clock synchronization

The I2C bus has a clock synchronization function to meet the transfer speed to a

slow processing device when a transfer is performed between device which have

different process speed.

The clock synchronization functions when the SCL pin is high level and the SCL

line of the bus is low level in the serial bus interface circuit. The serial bus

interface circuit waits counting a clock pulse in high level until the SCL line of the

bus is high level. When the SCL line of the bus is high level, the serial bus

interface circuit starts counting during high level. The clock synchronization

function holds clocks which are output from the serial interface circuit to be high

level.

The slave device can stop the clock output of the master device on one word or

one bit basis.

Additionally, the transfer speed by the master device matches to the process

speed of the slave device.

Figure 3.10.8 Clock Synchronization

(4) Slave address and address recognition mode specification

To operate the TMP93CS44/S45 in the addressing format which recognizes the slave

address, set I2CAR<ALS> to 0 and set the slave address to the I2CAR<SA6:0>.

To operate the serial bus interface circuit in the free data format which does not

recognize the slave address, set <ALS> to 1. When the TMP93CS44/S45 used in the

free data format, the slave address and the direction bit are not recognized. They are

handled as data just after generation of start conditions.

(5) Master/slave selection

Set SBICR2<MST> to 1 for operating the TMP93CS44/S45 as a master device.

<MST> is cleared to 0 by the hardware after a stop condition on a bus is detected.

Wait

Start counting high-level width of a

clock pulse

SCL pin (Master device)

SCL pin (Slave device)

SCL (Bus)

TMP93CS44 Datasheet(PDF) 156 Page - Toshiba Semiconductor