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TMP93CS44 Datasheet(PDF) 165 Page - Toshiba Semiconductor |
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TMP93CS44 Datasheet(HTML) 165 Page - Toshiba Semiconductor |
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165 / 224 page ![]() TMP93CS44/S45 2004-02-10 93CS44-163 (4) Stop condition generation When SBISR<BB> is 1, a sequence of generating a stop condition is started by writing 1 to SBICR2<MST, TRX, PIN>, and 0 to <BB>. Do not modify the contents of <MST, TRX, BB, PIN> until the stop condition is generated on the bus. When SBICR2<MST, TRX, PIN> are written “1” and <BB> is written “0” (generate stop condition in master mode), <BB> changes to “0” by internal SCL changes to “1”, without waiting stop condition. To check whether SCL and SDA pin are “1” by sensing their ports is needed to detect bus free condition. Figure 3.10.16 Stop Condition Generation Stop condition Internal SCL SDA pin <PIN> <BB> (Read) “1” → <MST> “1” → <TRX> “0” → <BB> “1” → <PIN> SCL pin |
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