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TMP93CS44 Datasheet(PDF) 197 Page - Toshiba Semiconductor |
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TMP93CS44 Datasheet(HTML) 197 Page - Toshiba Semiconductor |
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197 / 224 page  TMP93CS44/S45 2004-02-10 93CS44-195 4.4 Serial Channel Timing (1) I/O interface mode 1. SCLK input mode Variable (Note 1) 32.768 MHz 12.5 MHz 20 MHz Parameter Symbol Min Max Min Max Min Max Min Max Unit SCLK cycke tSCY 16X 488 µs 1.28 µs 0.8 µs ns Output data → Falling edge of SCLK tOSS tSCY/2 − 5X − 50 91.5 µs 190 100 ns SCLK rising/falling edge → Output data hold tOHS 5X − 100 152 µs 300 150 ns SCLK rising/falling edge → Input data hold (Note 2) tHSR 0 0 0 0 ns SCLK rising/falling edge → Effective data input (Note 2) tSRD tSCY − 5X − 100 336 µs 780 450 ns Note 1: When fs is used as system clock or fs divided by 4 is used as input clock to prescaler. Note 2: SCLK rising/falling timing; SCLK rising in the rising mode of SCLK, SCLK falling in the falling mode of SCLK. 2. SCLK output mode Variable (Note) 32.768 MHz 12.5 MHz 20 MHz Parameter Symbol Min Max Min Max Min Max Min Max Unit SCLK cycle (Programmable) tSCY 16X 8192X 488 µs 250 ms 1.28 µs 655.36 µs 0.8 µs 409.6 µsns Output data → SCLK rising edge tOSS tSCY − 2X − 150 427 µs 970 550 ns SCLK rising edge → Output data hold tOHS 2X − 80 60 µs 80 20 ns SCLK rising edge → Input data hold tHSR 0 0 0 0 ns SCLK rising edge → Effective data input tSRD tSCY − 2X − 150 428 µs 970 550 ns Note: When fs is used as system clock or fs divided by 4 is used as input clock to prescaler. (2) UART mode (SCLK0 and SCLK1 are external input) Variable (Note) 32.768 MHz 12.5 MHz 20 MHz Parameter Symbol Min Max Min Max Min Max Min Max Unit SCLK cycle tSCY 4X + 20 122 µs 340 220 ns SCLK low level pulse width tSCYL 2X + 5 6 µs 165 105 ns SCLK high level pulse width tSCYH 2X + 5 6 µs 165 105 ns Note: When fs is used as system clock or fs divided by 4 is used as input clock to prescaler. 0 SCLK (Input falling edge mode) Output data TXD SCLK Output mode/ input rising edge mode 123 3 2 1 0 tSCY tOSS tOHS tSRD tHSR Valid Valid Valid Valid Input data RXD |
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