All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

tation. It also permits FPGA prototyping be-

fore ASIC production.

Unlimited Designs

license allows using IP

Core in unlimited number of FPGA bitstreams

and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time of use

limitations.

●

○

Single Design license for

VHDL, Verilog source code called HDL

Source

Encrypted, or plain text EDIF called Netlist

○

●

○

○

●

○

○

Unlimited Designs license for

HDL Source

Netlist

Upgrade from

Netlist to HDL Source

Single Design to Unlimited Designs

SYMBOL

adatai(31:0)

bdatai(31:0)

datao(31:0)

en

rst

clk

ofo

ufo

ifo

PINS DESCRIPTI O N

PIN

TYPE

DESCRIPTION

clk

Input Global system clock

rst

Input Global system reset

en

Input Enable computing

adatai[31:0]

Input A data bus input

bdatai[31:0]

Input B data bus input

datao[31:0]

Output Data bus output

ofo

Output Overflow flag

ufo

Output Underflow flag

ifo

Output Invalid result flag

BLOCK DIAGRAM

bdatai(31:0)

datao(31:0)

en

rst

clk

ofo

ufo

ifo

Arguments

Checker

Main FP

Pipelined Unit

Result

Composer

adatai(31:0)

Arguments Checker

- performs input data

analyze against IEEE-754 number standard

compliance. The appropriate numbers and

information about the input data classes are

given as the results to Main FP Pipelined

Unit.

Main FP Pipelined Unit

- performs floating

point divide function. Gives the complex in-

formation about the results and makes final

flags settings.

Result Composer

- performs result rounding

function, data alignment to IEEE-754 stan-

dard, and the final flags setting.

PERFORMANCE

The following table gives a survey about the

Core area and performance in the ALTERA®

devices after Place & Route :

Device

Speed

grade

Logic

Cells

FLEX10KE

-1

3100

30 MHz

ACEX1K

-1

3100

30 MHz

APEX20K

-1

2720

40 MHz

APEX20KE

-1

2720

40 MHz

APEX20KC

-7

2720

42 MHz

APEX-II

-7

2720

50 MHz

MERCURY

-5

2780

65 MHz

STRATIX

-5

2270

88 MHz

CYCLONE

-6

2270

86 MHz

STRATIX-II

-3

2040

104 MHz

Core performance in ALTERA® devices