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DFPSQRT Datasheet(PDF) 2 Page - Digital Core Design

Part # DFPSQRT
Description  Floating Point Pipelined Square Root Unit
PDF  3 Pages
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Manufacturer  DCD [Digital Core Design]
Direct Link  http://www.digitalcoredesign.com
Logo DCD - Digital Core Design

DFPSQRT Datasheet(HTML) 2 Page - Digital Core Design

  DFPSQRT Datasheet HTML 1Page - Digital Core Design DFPSQRT Datasheet HTML 2Page - Digital Core Design DFPSQRT Datasheet HTML 3Page - Digital Core Design  
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All trademarks mentioned in this document
are trademarks of their respective owners.
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
tation. It also permits FPGA prototyping be-
fore ASIC production.
Unlimited Designs
license allows using IP
Core in unlimited number of FPGA bitstreams
and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time of use
limitations.
●
○
Single Design license for
VHDL, Verilog source code called HDL
Source
Encrypted, or plain text EDIF called Netlist
○
●
○
○
●
○
○
Unlimited Designs license for
HDL Source
Netlist
Upgrade from
Netlist to HDL Source
Single Design to Unlimited Designs
SYMBOL
datai(31:0)
datao(31:0)
en
rst
clk
ofo
ufo
ifo
PINS DESCRIPTI O N
PIN
TYPE
DESCRIPTION
clk
Input Global system clock
rst
Input Global system reset
en
Input Enable computing
datai[31:0]
Input Data bus input
datao[31:0]
Output Data bus output
ofo
Output Overflow flag
ufo
Output Underflow flag
ifo
Output Invalid result flag
BLOCK DIAGRAM
datai(31:0)
datao(31:0)
en
rst
clk
ofo
ufo
ifo
Argument
Checker
Main FP
Pipelined Unit
Result
Composer
Arguments Checker
- performs input data
analyze against IEEE-754 number standard
compliance. The appropriate numbers and
information about the input data classes are
given as the results to Main FP Pipelined
Unit.
Main FP Pipelined Unit
- performs floating
point square root function. Gives the complex
information about the results to Result Com-
poser module.
Result Composer
- performs result rounding
function, data alignment to IEEE-754 stan-
dard, and the final flags setting.
PERFORMANCE
The following table gives a survey about the
Core area and performance in the ALTERA®
devices after Place & Route :
Device
Speed
grade
Logic Cells
Fmax
FLEX10KE
-1
1000
48 MHz
ACEX1K
-1
1000
48 MHz
APEX20K
-1
970
50 MHz
APEX20KE
-1
970
53 MHz
APEX20KC
-7
970
62 MHz
APEX-II
-7
970
83 MHz
MERCURY
-5
975
99 MHz
STRATIX
-5
725
96 MHz
CYCLONE
-6
725
94 MHz
STRATIX-II
-3
890
131 MHz
CYCLONE-II
-6
730
99 MHz
Core performance in ALTERA® devices



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