All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2006 DCD – Digital Core Design. All Rights Reserved.

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http://www.DigitalCoreDesign.com

http://www.dcd.pl

ALU

- Arithmetic Logic Unit performs the arith-

metic and logic operations during execution of

an instruction. Contains accumulator CPU reg-

isters and related logic such as arithmetic and

logic unit. ALU communicates with internal reg-

isters and the external data bus by using inter-

nal data bus. Functions performed by the ALU

include:

Addition

Subtraction

Logical AND

Logical OR

Logical Exclusive OR

Compare

Left or Right Shifts or Rotates

Increment

Decrement

Set/Reset and Test Bit

datai

clk

rst

datao

BUS

Controller

Opcode

Decoder

Control

Unit

Interrupt

Controller

int

nmi

rd

wr

addr

iorq

rfsh

ALU

busack

busrq

wait

m1

mreq

halt

Bus Controller

–Data Memory & SFR’s (Spe-

cial Function Register) interface controls access

into the program and data memories and spe-

cial registers. It contains Program Counter

(PC), Stack Pointer (SP) register, Index regis-

ters and related logic.

Interrupt Controller

– manages execution of

maskable and nonmaskable interrupts. It con-

tains a Interrupt Enable register. Interrupt con-

troller is responsible for the special M1 Cycle

generation and wait states implementation dur-

ing interrupt service.

CONTACTS

For any modification or special request

please contact to Digital Core Design or local

distributors.

Headquarters:

Wroclawska 94

41-902 Bytom, POLAND

e-mail:

info@dcd.pl

iinnffoo@

@ddccdd..ppll

tel.

:

+48 32 282 82 66

fax

:

+48 32 282 74 37

Distributors:

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