TMP86FS49AIUG datasheet(78/296 Pages) TOSHIBA

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Page 62

5. I/O Ports

5.8 Port P7 (P77 to P70)

TMP86FS49AIUG

5.8

Port P7 (P77 to P70)

Port P7 is an 8-bit input/output port which can be configured as an input or output in one-bit unit.

Port P7 is also used as an analog input.

Input/output mode is specified by the P7 control register (P7CR1) and P7 input control register (P7CR2).

During reset, the P7CR1 is initialized to "0" the P7CR2 is initialized to "1" and port P7 becomes an input mode.

And the P7DR is initialized to "0".

When used as an output port, the corresponding bit of P7CR1 should be set to "1".

When used as an input port, the corresponding bit of P7CR1 should be set to "0" and then, the corresponding bit of

P7CR2 should be set to "1".

When used as an analog input, the corresponding bit of P7CR1 should be set to "0" and then, the corresponding bit

of P7CR2 should be set to "0".

When P7CR1 is "1", the content of the corresponding output latch is read by reading P7DR.

Note: Asterisk (*) indicates “1” or “0” either of which can be selected.

Table 5-6

Function

Programmed Value

P7DR

P7CR1

P7CR2

Port input external interrupt input or key-on wakeup

input

*“0”

“1”

Analog input

“0”

Port “0” output

“0”

“1”

Port “1” output

“1”

Table 5-7

Values Read from P7DR and Register Programming

Conditions

Values Read from P7DR

P7CR1

P7CR2

“0”

“1”

Terminal input data

“1”

“0”

Output latch contents

“1”

TMP86FS49AIUG Datasheet(PDF) 78 Page - Toshiba Semiconductor

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