8.4 Layout

8.4.1 Layout Guidelines

Attention to good layout practices is always recommended. For best operational performance of the device, use

good PCB layout practices, including:

• Make sure that both input paths are well-matched for source impedance and capacitance to avoid converting

common-mode signals into differential signals.

• Noise propagates into analog circuitry through the power pins of the circuit as a whole and of the device.

Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the analog

circuitry.

– Connect low-ESR, 0.1µF ceramic bypass capacitors between each supply pin and ground and place the

capacitors as close as possible to the device. A single bypass capacitor from V+ to ground is applicable

for single-supply applications.

• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible.

If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better than in

parallel with the noisy trace.

• Place the external components as close to the device as possible. As shown in Figure 8-6.

• Keep the traces as short as possible.

8.4.2 Layout Examples

+IN

-IN

+V

OUT

-V

C1

C2

INA630

R1

R2

R3

R3 = R1 || R2

INP

INN

R4

R5

C3

C4

C5

Figure 8-5. Example Schematic

NC

8

+VS

INN

7

OUT

INP

6

FB

4

VS

5

REF

1

2

3

GND

+IN

–IN

GND

+V

C2

C1

Place bypass

capacitors as close to

IC as possible

R1

R2

R3

V

C1

R5

R4

C5

C4

C3

R1

R2

Figure 8-6. Associated PCB Layout

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INA630

SBOSAI8 – MARCH 2025

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