Data Sheet

AD8488

Rev. A | Page 17 of 20

TIMING DIAGRAMS

t1

DATA

WR

t3

t2

t4

t5

t6

NOTES

1. TIMING DIAGRAM TO WRITE A STATIC SIGNAL TO CHANNEL 0 TO CHANNEL 63

OR CHANNEL 64 TO CHANNEL127.

2. CS_A LOW OR CS_B LOW SELECTS CHANNEL 0 TO CHANNEL 63 OR CHANNEL 64

TO CHANNEL 127. WRITE DATA BY SEQUENCING WR LOW, THEN HIGH.

CS_A, CS_B

Figure 18. Input Register Timing Diagram

CLK

tCLK

ADC INPUT

001

tDELAY7

tDELAY8

SAMPLE

SETTLES

NOTES

1. ADC SAMPLES OCCUR WHEN MUX-CH001 TO MUX-CH003 IS HIGH, JUST PRIOR TO THE FALLING EDGE.

SAMPLE MUST BE COMPLETE BEFORE HIGH TO LOW TRANSITION.

2. TIME DELAY SAMPLES (REFERENCE, INTERNAL ONLY):

MIN.

TYP.

MAX.

tDELAY 7:

5.3ns

6.6ns

7.8ns

tDELAY 8:

1.2ns

1.4ns

1.7ns

3.

tA IS SYNCHRONOUS WITH ADC TIMING.

ADC SAMPLE

MUX-CH001

ADC SAMPLE

MUX-CH002

ADC SAMPLE

MUX-CH003

002

003

MUX-CH001

TO

MUX-CH003

Figure 19. Timing Diagram—AD8488 to ADC