Timing Diagrams (Continued)

FIGURE 12. TIMING DIAGRAM-DECADE MODE

FIGURE 13. CASCADING COUNTER PACKAGES

0

1

2

345

6

7

8

9

8

7

6

5

43

2

100

9

8

7

CLOCK (CL)

CARRY IN

(CL ENABLE)

UP/DOWN

BINARY/

PRESET

ENABLE

J1

J2

J3

J4

Q1

Q2

Q3

Q4

CARRY OUT

COUNT

DECADE

*CARRY OUT LINES AT THE 2ND, 3RD, ETC, STAGES MAY HAVE A NEG-

ATIVE-GOING

GLITCH

PULSE

RESULTING

FROM

DIFFERENTIAL

DELAYS OF DIFFERENT CD4029BMS IC’S. THESE NEGATIVE GOING

GLITCHES DO NOT AFFECT PROPER CD4029BMS OPERATION. HOW-

EVER, IF THE CARRY OUT SIGNALS ARE USED TO TRIGGER OTHER

EDGE-SENSITIVE LOGIC DEVICES, SUCH AS FF’S OR COUNTERS, THE

CARRY OUT SIGNALS SHOULD BE GATED WITH THE CLOCK SIGNAL

USING A 2-INPUT OR GATE SUCH AS CD4071BMS.

UP/D

B/D

PE

CL Q1 Q2 Q3 Q4

CI

CO

J1 J2 J3 J4

CD4029

UP/D

B/D

PE

CL Q1 Q2 Q3 Q4

CI

CO

J1 J2 J3 J4

CD4029

UP/D

B/D

PE

CL Q1 Q2 Q3 Q4

CI

CO

J1 J2 J3 J4

CD4029

*

UP/DOWN

PRESET

ENABLE

CLOCK

BINARY/

DECADE

“PARALLEL CLOCKING”

CD4029BMS

www.sycelectronica.com.ar