ACT43750 datasheet(29/43 Pages) QORVO

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Data Sheet Rev. F, February 10, 2025 | Subject to change without notice

29 of 43

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ACT43750

RF POL Drain-Switch Driver / Gate-bias Regulator

REGG Enable Input Logic external

The ACT43750 provides two methods to turn the REGG

block ON and OFF.

Hardware Enable Pin. Enable the REGG block by ap-

plying a logic H to the ENG pin (enable gate). Disable

REGG by applying a logic low to ENG.

I2C Slave Bus. Enable the REGG block by writing a 1

into the EN_REGG bit in register 0x08h [7]. Disable

REGG by writing a 1 into the DIS_REGG bit in register

0x08h [6].

Note that the EN_REGG and DIS_REGG bits are auto-

matically cleared after the I2C write. Reading these two

bits always returns a 0.

The IC uses the logic OR of the ENG pin and the I2C

registers to enable the IC. Pulling the ENG pin high or

writing 1 to EN_REGG enables the REGG block. Pull-

ing the ENG pin low disables the REGG block. Writing

a 1 into DIS_REGG disables the REGG block, even if

ENG is high.

REGG Soft start

The REGG soft start is controlled by the CGREF capacitor

on the GREF pin by applying a constant current output

to this capacitor at startup. The soft start time can be

increased or decreased by adjusting the CGREF capaci-

tor value or by adjusting the constant current output.

The constant current output is controlled to 5µA, 10µA,

100µA, or 200µA by the IchgGREF bits in register

0x0Eh. Reducing the soft start time requires higher out-

put current and a higher peak current in the gate drive

supply inductor. Qorvo recommends keeping the gate

current below 500mA during softstart.

Idq Bias Point Calibration

The ACT43750 provides a calibration routine that cali-

brates the proper RF PA gate voltage bias point. The

calibration routine operates in the RSCAL State. The

typical RF PA datasheet provides an Idq value that de-

fines the proper drain current with no RF applied. This

drain current is achieved by properly controlling the RF

PA gate voltage. The ACT43750 autocalibration routine

sweeps the negative gate voltage while measuring Idq.

When the RF PA sinks the proper Idq, the IC saves the

resulting gate voltage in registers 0x06h and 0x07h and

uses that value to bias the RF PA.

The bias point calibration routine utilizes a dedicated

FET and current sense resistor that is sized for the re-

quired Idq current. When the routine is enabled, the IC

turns off the main drain FET, TRHS. The actual autocali-

bration routine depends on the previous state of the

system. The following equation calculates the correct

calibration resistor value to bias the RF PA to the cor-

rect Idq.

�� =

1.5��

��

(2)

Where:

Idq

– RFPA dc bias current, unit A

Rscal-

Calibration resistor, unit Ω

Initial Calibration Routine. For the first calibration rou-

tine after power up, the IC sets the DACG voltage to the

value defined by DACGMAX, which sets the gate volt-

age, VG, to the farthest negative value. This ensures

that the RF PA is in pinch-off when the drain voltage is

applied. At this time, no current flows through the FET

or current sense resistor. It then turns on the smaller

calibration FET, TRSMALL, and starts sweeping the DACG

voltage lower, which makes the VG gate voltage go

higher (more positive). Note that gate voltage is nega-

tive two times the DAC voltage. This starts increasing

the Idq to the desired setpoint. The IC decreases DACG

voltage one step at a time with the delay time between

steps set by the DACG Servo settings. When the cor-

rect Idq current is reached, the REGG voltage is held

constant and the corresponding DACG value is saved

in registers 0x06h and 0x07h. The IC automatically

moves to the TX Ready State.

The ACT43750 measures the Idq current by sensing the

voltage across the current sense calibration resistor,

RSCAL. It compares this voltage to a 1.5V internal refer-

ence threshold, VIT+(CSCAL). Note that the current sense

voltage is measured between the V50 and CSCAL pins.

Qorvo recommends connecting a

20kΩ Rcal resistor

between CSCAL and the TRSMALL FET. Connect a

100nF filter capacitor across RSCAL and the filter capac-

itor as shown in Figure 8.

The calibration routine can be started by either applying

a logic H to the ENCAL pin or by writing a 1 into the

RunCal bit in register 0x08h [3]. The RunCal bit is auto-

matically cleared back to a 0 when the calibration rou-

tine starts. The typical auto calibration time is approxi-

mately 30ms. This can be increased or decreased by

changing the starting gate voltage and by adjusting

DAC servo speed control. The actual calibration time

depends on the bias voltage starting point and the

DACG digital servo speed control. Register 0x10h pro-

grams DACG voltage transition time, which will make

the calibration time shorter or longer.

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