7

Cross Trigger Interface

The processor includes an optional Cross Trigger Interface Unit which includes an interface suitable

for connection to external CoreSight components using a Cross Trigger Matrix.

MBIST Interface

The MBIST Interface is used for testing the RAMs during production test. The Cortex-M7

processor also allows the RAMs to be tested using the MBIST interface during normal execution.

This is known as online MBIST.

AXIM Interface

The AXIM interface provides high-performance access to an external memory system. The AXIM

interface supports use of the Arm CoreLink L2C-310 Level 2 Cache Controller. L2C-310 exclusive

cache configuration is not supported.

Cortex-M7 Processor Pipeline

6-stage, in order, superscalar pipeline

Integer pipe:

– Dual shifters, dual ALUs, one MAC-capable

Float pipe:

– FP instructions can be dual issued with integer instructions

– BTAC and branch predictor boost performance

Figure 3: Cortex-M7

processor pipeline