AD7124-8BBCPZ datasheet(83/95 Pages) AD

83 / 95 page

Data Sheet

AD7124-8

ON-CHIP REGISTERS

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Rev. F | 83 of 95

Table 68. Operating Modes (Continued)

Mode Value Description

0110

Internal full-scale (gain) calibration. A full-scale input voltage is automatically connected to the selected analog input for this calibration. RDY goes high when

the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale

coefficient is placed in the gain register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize

the full-scale error. Select only one channel when full-scale calibration is being performed. The AD7124-8 is factory calibrated at a gain of 1. Further internal

full‑scale calibrations at a gain of 1 are not supported. An internal full-scale calibration (gain > 1) takes a time of four settling periods.

Internal full-scale calibrations cannot be performed in the full power mode. So, if using the full-power mode, select mid or low power mode for the internal

full-scale calibration. This calibration is valid in full power mode as the same reference and gain are used. When performing internal zero-scale and internal

full-scale calibrations, the internal full-scale calibration must be performed before the internal zero-scale calibration. Therefore, write 0x800000 to the offset

0111

System zero-scale (offset) calibration. Connect the system zero-scale input to the channel input pins of the selected channel. RDY goes high when the

calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient

is placed in the offset register of the selected channel. A system zero-scale calibration is required each time the gain of a channel is changed. Select only one

channel when full-scale calibration is being performed. A system zero-scale calibration takes a time of one settling period to be performed.

1000

System full-scale (gain) calibration. Connect the system full-scale input to the channel input pins of the selected channel. RDY goes high when the calibration is

initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in

the gain register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed. Select only one channel when full-scale

calibration is being performed. A system full-scale calibration takes a time of one settling period to be performed.

1001 to1111 Reserved.

DATA REGISTER

RS[5:0] = 0, 0, 0, 0, 1, 0

Power-On/Reset = 0x000000

The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from this

IO_CONTROL_1 REGISTER

RS[5:0] = 0, 0, 0, 0, 1, 1

Power-On/Reset = 0x000000

Table 69 outlines the bit designations for the register. Bit 23 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GPIO_DAT4 (0)

GPIO_DAT3 (0)

GPIO_DAT2 (0)

GPIO_DAT1 (0)

GPIO_CTRL4 (0)

GPIO_CTRL3 (0)

GPIO_CTRL2 (0)

GPIO_CTRL1 (0)

PDSW (0)

0 (0)

IOUT1 (0)

IOUT0 (0)

IOUT1_CH (0)

IOUT0_CH (0)

Table 69. IO_CONTROL_1 Register Bit Descriptions

Bits

Bit Name

Description

GPIO_DAT4

Digital Output P4. When GPIO_CTRL4 is set, the GPIO_DAT4 bit sets the value of the P4 general-purpose output pin. When

GPIO_DAT4 is high, the P4 output pin is high. When GPIO_DAT4 is low, the P4 output pin is low. When the IO_CONTROL_1

GPIO_DAT3

Digital Output P3. When GPIO_CTRL3 is set, the GPIO_DAT3 bit sets the value of the P3 general-purpose output pin. When

GPIO_DAT3 is high, the P3 output pin is high. When GPIO_DAT3 is low, the P3 output pin is low. When the IO_CONTROL_1

GPIO_DAT2

Digital Output P2. When GPIO_CTRL2 is set, the GPIO_DAT2 bit sets the value of the P2 general-purpose output pin. When

GPIO_DAT2 is high, the P2 output pin is high. When GPIO_DAT2 is low, the P2 output pin is low. When the IO_CONTROL_1

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