Data Sheet

ADBMS6821/ADBMS6822

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. B | 10 of 28

Figure 4. ADBMS6822 Pin Configuration

Table 16. ADBMS6822 Pin Function Descriptions

Pin Number

Mnemonic

Description

1, 25

MSTR, MSTR2

SPI Mode Select. These pins select SPI controller mode (MSTR connected to VDDS and MSTR2 connected to VDDS2)

or peripheral mode (MSTR and MSTR2 connected to GND).

2, 26

PICO, PICO2

SPI Controller Outputs (Controller Mode) or Peripheral Inputs (Peripheral Mode).

3, 27

POCI, POCI2

SPI Controller Inputs (Controller Mode) or Peripheral Outputs (Peripheral Mode).

4, 28

SCK, SCK2

SPI Clock Inputs (Controller) or Outputs (Peripheral).

5, 29

CS, CS2

Active Low SPI Chip-Select Inputs (Controller Mode) or Outputs (Peripheral Mode).

6, 30

VDDS, VDDS2

SPI Power-Supply Inputs (1.7 V to 5.5 V).

7, 31

INTR, INTR2

LPCM Interrupt Current-Limited Outputs.

8, 32

WAKE, WAKE2

Device Wake-Up State Current-Limited Outputs or Inputs.

9, 17

GND

Ground. The GND pins must be shorted together external to the IC.

10, 18

IM, IM2

Isolated Interface Minus Inputs/Outputs.

11, 19

IP, IP2

Isolated Interface Plus Inputs/Outputs.

12, 20

VDD, VDD2

isoSPI Power-Supply Inputs (3.0 V to 5.5 V).

13, 21

VP, VP2

High Voltage Power-Supply Inputs (3.0 V to 30 V).

14, 22

PHAPOL, PHAPOL2

Multilevel, Resistor Set SPI PHA/POL Selection Inputs.

15, 23

RTO, RTO2

Multilevel, Resistor Set LPCM Timeout Selection Inputs.

16, 24

XCVRMD, XCVRMD2

Multilevel, Resistor Set Transceiver Mode Selection Inputs.

33

EP

Exposed Pad. Must be connected to GND.