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ADF41510BCPZ Datasheet(PDF) 25 Page - Analog Devices

Part # ADF41510BCPZ
Description  10 GHz, Integer-N/Fractional-N PLL Synthesizer
PDF  29 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF41510BCPZ Datasheet(HTML) 25 Page - Analog Devices

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Data Sheet
ADF41510
REGISTER MAPS
analog.com
Rev. A | 25 of 29
REGISTER 12 (R12) MAP
MUXOUT
Register 12, Bits[31:28] select the MUXOUT signal. Register data
can be read either by selecting the serial data output or via a
readback. Serial data output sends the 32 bits of register data that
was written in the previous access. A readback sends the data as
defined by the readback select bits, Register 12, Bits[19:14].
Logic Level
Register 12, Bit 27 selects the DLD and MUXOUT logic level.
Main Reset
Register 12, Bit 22 = 1 resets all registers to all zeros.
LE Select
Register 12, Bit 20 = 1 synchronizes the rising edge of LE on
an SPI write with the falling edge of the reference signal. This
recommended setting ensures there is no glitch from asynchronous
loading. Set Register 12, Bit 20 = 0 if it is necessary to write data
into the ADF41510 when no reference is present.
Readback Select
Register 12, Bits[19:14] select the value to be read back. For more
information, see the Readback section.
Figure 33. Register 12 (R12) Map



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