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TC9318AFAG Datasheet(PDF) 49 Page - Toshiba Semiconductor |
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TC9318AFAG Datasheet(HTML) 49 Page - Toshiba Semiconductor |
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49 / 56 page  TC9318AFAG/AFBG 2006-07-27 49 2. MUTE Output Structure and Timing Note 50: When POL bit = 0 Note 51: When using the phase difference output by the phase comparator, externally connect a low-pass filter to the MUTE output. Test Ports These are internal ports for testing the device’s functions. Access the ports by executing the OUT1 instruction with the operand [CN = AH] or [CN = DH], or the OUT2 instruction with the operands [CN = FFH]. The ports are normally set to “0” by software. If the data “1” is set to Test port bit from #0 to #3, the CPU stop function is inhibited and the data “0” is set, the CPU function is operating. In case of using supply voltage detection externally, set CPU stop function as inhibition. Note 52: The ports are reset to “0” after a system reset. |
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