CDC2509C

3.3V PHASELOCK LOOP CLOCK DRIVER

SCAS620A − DECEMBER 1998 − REVISED DECEMBER 2004

2

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

description (continued)

For application information refer to application reports High Speed Distribution Design Techniques for

CDC509/516/2509/2510/2516 (literature number SLMA003) and Using CDC2509A/2510A PLL with Spread

Spectrum Clocking (SSC) (literature number SCAA039).

FUNCTION TABLE

INPUTS

OUTPUTS

1G

2G

CLK

1Y

(0:4)

2Y

(0:3)

FBOUT

X

X

L

L

L

L

L

LHL

LH

L

HH

L

HH

H

LH

H

LH

H

H

H

H

H

H

functional block diagram

1Y2

1Y1

1Y0

PLL

FBIN

AVCC

2G

CLK

1G

2Y2

2Y1

2Y0

2Y3

FBOUT

1Y3

1Y4

11

14

24

13

23

3

4

5

8

9

21

20

17

16

12

AVAILABLE OPTIONS