CY74FCT823T

9-BIT BUS-INTERFACE REGISTER

WITH 3-STATE OUTPUTS

SCCS069A – OCTOBER 2001 – REVISED NOVEMBER 2001

2

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

ORDERING INFORMATION

TA

PACKAGE†

SPEED

(ns)

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QSOP – Q

Tape and reel

6

CY74FCT823CTQCT

FCT823C

SOIC

SO

Tube

6

CY74FCT823CTSOC

FCT823C

SOIC – SO

Tape and reel

6

CY74FCT823CTSOCT

FCT823C

40

°Cto85°C

DIP – P

Tube

7.5

CY74FCT823BTPC

CY74FCT823BTPC

–40

°C to 85°C

DIP – P

Tube

10

CY74FCT823ATPC

CY74FCT823ATPC

QSOP – Q

Tape and reel

10

CY74FCT823ATQCT

FCT823A

SOIC

SO

Tube

10

CY74FCT823ATSOC

FCT823A

SOIC – SO

Tape and reel

10

CY74FCT823ATSOCT

FCT823A

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

PIN DESCRIPTION

NAME

I/O

DESCRIPTION

D

I

D flip-flop data inputs

CLR

I

When CLR is low and OE is low, Q outputs are low. When CLR is high, data can be entered into the register.

CP

O

Clock pulse for the register. Enters data into the register on the low-to-high clock transition.

Y

O

Register 3-state outputs

EN

I

Clock enable. When EN is low, data on the D input is transferred to the Q output on the low-to-high clock transition. When

EN is high, the Q outputs do not change state, regardless of the data or clock input transitions.

OE

I

Output control. When OE is high, the Y outputs are in the high-impedance state. When OE is low, true register data is present

at the Y outputs.

FUNCTION TABLE

INPUTS

INTERNAL

OUTPUTS

FUNCTION

OE

CLR

EN

D

CP

Q

Y

H

H

L

L

↑

L

Z

Z

H

HL

H

↑

H

Z

Z

H

L

X

X

X

L

Z

Clear

L

LX

X

XL

L

Clear

H

H

H

X

X

NC

Z

Hold

L

HH

X

XNC

NC

Hold

H

H

L

L

↑

L

Z

H

HL

H

↑

H

Z

Load

L

HL

L

↑

L

L

Load

L

H

L

H

↑

H

H

H = High logic level, L = Low logic level, X = Don’t care, NC = No change,

↑ = Low-to-high transition, Z = High-impedance state