CY54FCT841T, CY74FCT841T

10-BIT LATCHES

WITH 3-STATE OUTPUTS

SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001

2

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

ORDERING INFORMATION

TA

PACKAGE†

SPEED

(ns)

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QSOP – Q

Tape and reel

5.5

CY74FCT841CTQCT

FCT841C

SOIC

SO

Tube

5.5

CY74FCT841CTSOC

FCT841C

40

°Cto85°C

SOIC – SO

Tape and reel

5.5

CY74FCT841CTSOCT

FCT841C

–40

°C to 85°C

DIP – P

Tube

6.5

CY74FCT841BTPC

CY74FCT841BTPC

SOIC

SO

Tube

9

CY74FCT841ATSOC

FCT841A

SOIC – SO

Tape and reel

9

CY74FCT841ATSOCT

FCT841A

–55

°C to 125°C

CDIP – D

Tube

10

CY54FCT841ATDMB

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE

INPUTS

INTERNAL

OUTPUTS

FUNCTION

OE

LE

D

O

Y

H

X

X

X

Z

H

HL

L

ZZ

H

HH

H

Z

H

L

X

NC

Z

Latched (Z)

L

H

L

L

L

Transparent

L

HH

H

H

Transparent

L

L

X

NC

NC

Latched

H = High logic level, L = Low logic level, X = Don’t care,

NC = No change, Z = High-impedance state

logic diagram (positive logic)

OE

To Nine Other Channels

1

13

2

23

LE

D0

LE

D

Y0

Q