CSD87384M

www.ti.com

SLPS415D – SEPTEMBER 2013 – REVISED MARCH 2015

7 Layout

7.1 Layout Guidelines

7.1.1 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and

thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. A brief

description on how to address each parameter is provided.

7.1.2 Electrical Performance

The CSD87384M has the ability to switch voltages at rates greater than 10 kV/µs. Take special care with the

PCB layout design and placement of the input capacitors, inductor, and output capacitors.

•

The placement of the input capacitors relative to VIN and PGND pins of CSD87384M device should have the

highest priority during the component placement routine. It is critical to minimize these node lengths. As such,

ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 29).

The example in Figure 29 uses 1 × 10 nF 0402 25 V and 4 × 10

μF 1206 25 V ceramic capacitors (TDK part

number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board

with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the

Power Stage C21, C5, C8, C19, and C18 should follow in order.

•

The switching node of the output inductor should be placed relatively close to the Power Block II CSD87384M

VSW pins. Minimizing the VSW node length between these two components will reduce the PCB conduction

losses and actually reduce the switching noise level. See Figure 29. (1)

7.1.3 Thermal Performance

The CSD87384M has the ability to utilize the PGND planes as the primary thermal path. As such, the use of

thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder

voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount

of solder attach that wicks down the via barrel:

•

Intentionally space out the vias from each other to avoid a cluster of holes in a given area.

•

Use the smallest drill size allowed in your design. The example in Figure 29 uses vias with a 10 mil drill hole

and a 16 mil capture pad.

•

Tent the opposite side of the via with solder-mask.

The number and drill size of the thermal vias should align with the end user’s PCB design rules and

manufacturing capabilities.

7.2 Layout Example

Figure 29. Recommended PCB Layout (Top Down View)

(1)

Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of

Missouri – Rolla

Copyright © 2013–2015, Texas Instruments Incorporated

Submit Documentation Feedback

13